1/* 2 * (C) Copyright 2001 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8/* 9 * board/config.h - configuration options, board specific 10 */ 11 12#ifndef __CONFIG_H 13#define __CONFIG_H 14 15/* 16 * High Level Configuration Options 17 * (easy to change) 18 */ 19 20#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ 21#define CONFIG_FLAGADM 1 /* ...on a FLAGA DM */ 22#define CONFIG_8xx_GCLK_FREQ 48000000 /*48MHz*/ 23 24#define CONFIG_SYS_TEXT_BASE 0x40000000 25 26#undef CONFIG_8xx_CONS_SMC1 /* Console is on SMC1 */ 27#define CONFIG_8xx_CONS_SMC2 1 28#undef CONFIG_8xx_CONS_NONE 29 30#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ 31#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ 32 33#undef CONFIG_CLOCKS_IN_MHZ 34 35#if 0 36#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=bootp" 37#define CONFIG_BOOTCOMMAND \ 38 "setenv bootargs root=/dev/ram ip=off panic=1;" \ 39 "bootm 40040000 400e0000" 40#else 41#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=bootp panic=1" 42#define CONFIG_BOOTCOMMAND "bootp 0x400000; bootm 0x400000" 43#endif /* 0|1*/ 44 45#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 46#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 47 48/*#define CONFIG_WATCHDOG*/ /* watchdog enabled */ 49#undef CONFIG_WATCHDOG /* watchdog disabled */ 50 51/* 52 * BOOTP options 53 */ 54#define CONFIG_BOOTP_SUBNETMASK 55#define CONFIG_BOOTP_GATEWAY 56#define CONFIG_BOOTP_HOSTNAME 57#define CONFIG_BOOTP_BOOTPATH 58#define CONFIG_BOOTP_BOOTFILESIZE 59 60 61/* 62 * Command line configuration. 63 */ 64 65#define CONFIG_CMD_BDI 66#define CONFIG_CMD_IMI 67#define CONFIG_CMD_CACHE 68#define CONFIG_CMD_MEMORY 69#define CONFIG_CMD_FLASH 70#define CONFIG_CMD_LOADB 71#define CONFIG_CMD_LOADS 72#define CONFIG_CMD_SAVEENV 73#define CONFIG_CMD_REGINFO 74#define CONFIG_CMD_IMMAP 75#define CONFIG_CMD_NET 76 77 78/* 79 * Miscellaneous configurable options 80 */ 81#define CONFIG_SYS_LONGHELP /* undef to save memory */ 82#define CONFIG_SYS_PROMPT "EEG> " /* Monitor Command Prompt */ 83#if defined(CONFIG_CMD_KGDB) 84#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 85#else 86#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 87#endif 88#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 89#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 90#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 91 92#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ 93#define CONFIG_SYS_MEMTEST_END 0x0f00000 /* 1 ... 15 MB in DRAM */ 94 95#define CONFIG_SYS_LOAD_ADDR 0x40040000 /* default load address */ 96 97#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 98 99/* 100 * Low Level Configuration Settings 101 * (address mappings, register initial values, etc.) 102 * You should know what you are doing if you make changes here. 103 */ 104/*----------------------------------------------------------------------- 105 * Internal Memory Mapped Register 106 */ 107#define CONFIG_SYS_IMMR 0xFF000000 108 109/*----------------------------------------------------------------------- 110 * Definitions for initial stack pointer and data area (in DPRAM) 111 */ 112#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 113#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ 114#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 115#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 116 117/*----------------------------------------------------------------------- 118 * Start addresses for the final memory configuration 119 * (Set up by the startup code) 120 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 121 */ 122#define CONFIG_SYS_SDRAM_BASE 0x00000000 123#define CONFIG_SYS_FLASH_BASE 0x40000000 124#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ 125#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 126#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 127 128/* 129 * For booting Linux, the board info and command line data 130 * have to be in the first 8 MB of memory, since this is 131 * the maximum mapped by the Linux kernel during initialization. 132 */ 133#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 134 135/*----------------------------------------------------------------------- 136 * FLASH organization 137 */ 138#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 139#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ 140 141#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */ 142#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 143 144#define CONFIG_ENV_IS_IN_FLASH 1 145/* This is a litlebit wasteful, but one sector is 128kb and we have to 146 * assigne a whole sector for the environment, so that we can safely 147 * erase and write it without disturbing the boot sector 148 */ 149#define CONFIG_ENV_OFFSET 0x20000 /* Offset of Environment Sector */ 150#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ 151 152/*----------------------------------------------------------------------- 153 * Cache Configuration 154 */ 155#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 156#if defined(CONFIG_CMD_KGDB) 157#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 158#endif 159#define CONFIG_SYS_DELAYED_ICACHE 1 /* enable ICache not before 160 * running in RAM. 161 */ 162 163/*----------------------------------------------------------------------- 164 * SYPCR - System Protection Control 11-9 165 * SYPCR can only be written once after reset! 166 *----------------------------------------------------------------------- 167 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 168 */ 169#ifdef CONFIG_WATCHDOG 170#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP) 171#else 172#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF) 173#endif 174 175/*----------------------------------------------------------------------- 176 * SIUMCR - SIU Module Configuration 11-6 177 *----------------------------------------------------------------------- 178 * PCMCIA config., multi-function pin tri-state 179 */ 180#define CONFIG_SYS_PRE_SIUMCR (SIUMCR_DBGC11 | SIUMCR_MPRE | \ 181 SIUMCR_MLRC01 | SIUMCR_GB5E) 182#define CONFIG_SYS_SIUMCR (CONFIG_SYS_PRE_SIUMCR | SIUMCR_DLK) 183 184/*----------------------------------------------------------------------- 185 * TBSCR - Time Base Status and Control 11-26 186 *----------------------------------------------------------------------- 187 * Clear Reference Interrupt Status, Timebase freezing enabled 188 */ 189#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 190 191/*----------------------------------------------------------------------- 192 * RTCSC - Real-Time Clock Status and Control Register 11-27 193 *----------------------------------------------------------------------- 194 */ 195#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 196 197/*----------------------------------------------------------------------- 198 * PISCR - Periodic Interrupt Status and Control 11-31 199 *----------------------------------------------------------------------- 200 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 201 */ 202#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 203 204/*----------------------------------------------------------------------- 205 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 206 *----------------------------------------------------------------------- 207 * Reset PLL lock status sticky bit, timer expired status bit and timer 208 * interrupt status bit miltiplier of 0x00b i.e. operation clock is 209 * 4MHz * (0x00b+1) = 4MHz * 12 = 48MHz 210 */ 211#define CONFIG_SYS_PLPRCR (0x00b00000 | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) 212 213/*----------------------------------------------------------------------- 214 * SCCR - System Clock and reset Control Register 15-27 215 *----------------------------------------------------------------------- 216 * Set clock output, timebase and RTC source and divider, 217 * power management and some other internal clocks 218 */ 219#define SCCR_MASK SCCR_EBDF11 220#define CONFIG_SYS_SCCR ( SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 221 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 222 SCCR_DFALCD00) 223 224#define CONFIG_SYS_DER 0 225 226/* 227 * In the Flaga DM we have: 228 * Flash on BR0/OR0/CS0a at 0x40000000 229 * Display on BR1/OR1/CS1 at 0x20000000 230 * SDRAM on BR2/OR2/CS2 at 0x00000000 231 * Free BR3/OR3/CS3 232 * DSP1 on BR4/OR4/CS4 at 0x80000000 233 * DSP2 on BR5/OR5/CS5 at 0xa0000000 234 * 235 * For now we just configure the Flash and the SDRAM and leave the others 236 * untouched. 237*/ 238 239#define CONFIG_SYS_FLASH_PROTECTION 0 240 241#define FLASH_BASE0 0x40000000 /* FLASH bank #0 */ 242 243/* used to re-map FLASH both when starting from SRAM or FLASH: 244 * restrict access enough to keep SRAM working (if any) 245 * but not too much to meddle with FLASH accesses 246 */ 247#define CONFIG_SYS_OR_AM 0xff000000 /* OR addr mask */ 248#define CONFIG_SYS_OR_ATM 0x00006000 249 250/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */ 251#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | \ 252 OR_SCY_3_CLK | OR_TRLX | OR_EHTR ) 253 254#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_OR_AM | CONFIG_SYS_OR_ATM | CONFIG_SYS_OR_TIMING_FLASH) 255#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0 & BR_BA_MSK) | BR_PS_16 | BR_V ) 256 257/* 258 * BR2 and OR2 (SDRAM) 259 * 260 */ 261#define SDRAM_BASE2 0x00000000 /* SDRAM bank #0 */ 262#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ 263 264/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 265#define CONFIG_SYS_OR_TIMING_SDRAM ( 0x00000800 ) 266 267#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM) 268#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2 & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 269 270#define CONFIG_SYS_BR2 CONFIG_SYS_BR2_PRELIM 271#define CONFIG_SYS_OR2 CONFIG_SYS_OR2_PRELIM 272 273/* 274 * MAMR settings for SDRAM 275 */ 276#define CONFIG_SYS_MAMR_48_SDR (CONFIG_SYS_MAMR_PTA | MAMR_WLFA_1X | MAMR_RLFA_1X \ 277 | MAMR_G0CLA_A11) 278 279/* 280 * Memory Periodic Timer Prescaler 281 */ 282 283/* periodic timer for refresh */ 284#define CONFIG_SYS_MAMR_PTA 0x0F000000 285 286/* 287 * BR4 and OR4 (DSP1) 288 * 289 * We do not wan't preliminary setup of the DSP, anyway we need the 290 * UPMB setup correctly before we can access the DSP. 291 * 292*/ 293#define DSP_BASE 0x80000000 294 295#define CONFIG_SYS_OR4 ( OR_AM_MSK | OR_CSNT_SAM | OR_BI | OR_G5LS) 296#define CONFIG_SYS_BR4 ( (DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_UPMB | BR_V ) 297 298#endif /* __CONFIG_H */ 299