1/* 2 * (C) Copyright 2000 3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 4 * Marius Groeger <mgroeger@sysgo.de> 5 * 6 * Configuation settings for the MBX8xx board. 7 * 8 * ----------------------------------------------------------------- 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11/* 12 * Changed 2002-10-01 13 * Added PCMCIA defines mostly taken from other U-Boot boards that 14 * have PCMCIA already working. If you find any bugs, incorrect assumptions 15 * feel free to fix them yourself and submit a patch. 16 * Rod Boyce <rod_boyce@stratexnet.com. 17 */ 18/* 19 * board/config.h - configuration options, board specific 20 */ 21 22#ifndef __CONFIG_H 23#define __CONFIG_H 24 25/* 26 * High Level Configuration Options 27 * (easy to change) 28 */ 29 30#define CONFIG_MPC860 1 /* This is a MPC860 CPU */ 31#define CONFIG_MBX 1 /* ...on an MBX module */ 32 33#define CONFIG_SYS_TEXT_BASE 0xfe000000 34 35#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 36#undef CONFIG_8xx_CONS_SMC2 37#undef CONFIG_8xx_CONS_NONE 38#define CONFIG_BAUDRATE 9600 39/* Define this to use the PCI bus */ 40#undef CONFIG_USE_PCI 41 42#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ 43#define CONFIG_8xx_GCLK_FREQ (50000000UL) 44#if 1 45#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ 46#else 47#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 48#endif 49#define CONFIG_BOOTCOMMAND "bootm 20000" /* autoboot command */ 50 51#define CONFIG_BOOTARGS "root=/dev/nfs rw " \ 52 "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \ 53 "nfsaddrs=10.0.0.99:10.0.0.2" 54 55#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 56#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 57 58#undef CONFIG_WATCHDOG /* watchdog disabled */ 59 60 61/* 62 * BOOTP options 63 */ 64#define CONFIG_BOOTP_BOOTFILESIZE 65#define CONFIG_BOOTP_BOOTPATH 66#define CONFIG_BOOTP_GATEWAY 67#define CONFIG_BOOTP_HOSTNAME 68 69 70/* 71 * Command line configuration. 72 */ 73#define CONFIG_CMD_NET 74#define CONFIG_CMD_SDRAM 75#define CONFIG_CMD_PCMCIA 76#define CONFIG_CMD_IDE 77 78 79#define CONFIG_DOS_PARTITION 80 81/* 82 * Miscellaneous configurable options 83 */ 84#define CONFIG_SYS_LONGHELP /* undef to save memory */ 85#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 86#undef CONFIG_SYS_HUSH_PARSER /* Hush parse for U-Boot */ 87#if defined(CONFIG_CMD_KGDB) 88#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 89#else 90#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 91#endif 92#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 93#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 94#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 95 96#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 97#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 98 99#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 100 101#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 102 103/* 104 * Low Level Configuration Settings 105 * (address mappings, register initial values, etc.) 106 * You should know what you are doing if you make changes here. 107 */ 108 109/*----------------------------------------------------------------------- 110 * Physical memory map as defined by the MBX PGM 111 */ 112#define CONFIG_SYS_IMMR 0xFA200000 /* Internal Memory Mapped Register*/ 113#define CONFIG_SYS_NVRAM_BASE 0xFA000000 /* NVRAM */ 114#define CONFIG_SYS_NVRAM_OR 0xffe00000 /* w/o speed dependent flags!! */ 115#define CONFIG_SYS_CSR_BASE 0xFA100000 /* Control/Status Registers */ 116#define CONFIG_SYS_PCIMEM_BASE 0x80000000 /* PCI I/O and Memory Spaces */ 117#define CONFIG_SYS_PCIMEM_OR 0xA0000108 118#define CONFIG_SYS_PCIBRIDGE_BASE 0xFA210000 /* PCI-Bus Bridge Registers */ 119#define CONFIG_SYS_PCIBRIDGE_OR 0xFFFF0108 120 121/*----------------------------------------------------------------------- 122 * Definitions for initial stack pointer and data area (in DPRAM) 123 */ 124#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 125#define CONFIG_SYS_INIT_RAM_SIZE 0x2f00 /* Size of used area in DPRAM */ 126#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 127#define CONFIG_SYS_INIT_VPD_SIZE 256 /* size in bytes reserved for vpd buffer */ 128#define CONFIG_SYS_INIT_VPD_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_VPD_SIZE) 129#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_VPD_OFFSET-8) 130 131/*----------------------------------------------------------------------- 132 * Offset in DPMEM where we keep the VPD data 133 */ 134#define CONFIG_SYS_DPRAMVPD (CONFIG_SYS_INIT_VPD_OFFSET - 0x2000) 135 136/*----------------------------------------------------------------------- 137 * Start addresses for the final memory configuration 138 * (Set up by the startup code) 139 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 140 */ 141#define CONFIG_SYS_SDRAM_BASE 0x00000000 142#define CONFIG_SYS_FLASH_BASE 0xfe000000 143#ifdef DEBUG 144#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 145#else 146#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 147#endif 148#undef CONFIG_SYS_MONITOR_BASE /* 0x200000 to run U-Boot from RAM */ 149#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 150#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 151 152/* 153 * For booting Linux, the board info and command line data 154 * have to be in the first 8 MB of memory, since this is 155 * the maximum mapped by the Linux kernel during initialization. 156 */ 157#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 158 159/*----------------------------------------------------------------------- 160 * FLASH organization 161 */ 162#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 163#define CONFIG_SYS_MAX_FLASH_SECT 16 /* max number of sectors on one chip */ 164 165#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 166#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 167 168/*----------------------------------------------------------------------- 169 * NVRAM Configuration 170 * 171 * Note: the MBX is special because there is already a firmware on this 172 * board: EPPC-Bug from Motorola. To avoid collisions in NVRAM Usage, we 173 * access the NVRAM at the offset 0x1000. 174 */ 175#define CONFIG_ENV_IS_IN_NVRAM 1 /* turn on NVRAM env feature */ 176#define CONFIG_ENV_ADDR (CONFIG_SYS_NVRAM_BASE + 0x1000) 177#define CONFIG_ENV_SIZE 0x1000 178 179/*----------------------------------------------------------------------- 180 * Cache Configuration 181 */ 182#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 183#if defined(CONFIG_CMD_KGDB) 184#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 185#endif 186 187/*----------------------------------------------------------------------- 188 * SYPCR - System Protection Control 11-9 189 * SYPCR can only be written once after reset! 190 *----------------------------------------------------------------------- 191 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 192 */ 193#if defined(CONFIG_WATCHDOG) 194#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 195 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 196#else 197#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF) 198#endif 199 200/*----------------------------------------------------------------------- 201 * SIUMCR - SIU Module Configuration 11-6 202 *----------------------------------------------------------------------- 203 * PCMCIA config., multi-function pin tri-state 204 */ 205/* #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC10 | SIUMCR_SEME) */ 206#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC11 | SIUMCR_SEME | SIUMCR_BSC ) 207 208/*----------------------------------------------------------------------- 209 * TBSCR - Time Base Status and Control 11-26 210 *----------------------------------------------------------------------- 211 * Clear Reference Interrupt Status, Timebase freezing enabled 212 */ 213#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 214 215/*----------------------------------------------------------------------- 216 * PISCR - Periodic Interrupt Status and Control 11-31 217 *----------------------------------------------------------------------- 218 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 219 */ 220#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) 221 222/*----------------------------------------------------------------------- 223 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 224 *----------------------------------------------------------------------- 225 * Reset PLL lock status sticky bit, timer expired status bit and timer 226 * interrupt status bit - leave PLL multiplication factor unchanged ! 227 */ 228#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) 229 230/*----------------------------------------------------------------------- 231 * SCCR - System Clock and reset Control Register 15-27 232 *----------------------------------------------------------------------- 233 * Set clock output, timebase and RTC source and divider, 234 * power management and some other internal clocks 235 */ 236#define SCCR_MASK (SCCR_RTDIV | SCCR_RTSEL) 237#define CONFIG_SYS_SCCR SCCR_TBS 238 239/*----------------------------------------------------------------------- 240 * PCMCIA stuff 241 *----------------------------------------------------------------------- 242 * 243 */ 244#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 245#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 246#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 247#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 248#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 249#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 250#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 251#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 252 253#define CONFIG_SYS_PCMCIA_INTERRUPT SIU_LEVEL6 254 255#define CONFIG_PCMCIA_SLOT_A 1 256 257 258/*----------------------------------------------------------------------- 259 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) 260 *----------------------------------------------------------------------- 261 */ 262 263#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ 264#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ 265 266#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 267#undef CONFIG_IDE_LED /* LED for ide not supported */ 268#undef CONFIG_IDE_RESET /* reset for ide not supported */ 269 270#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 271#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 272 273#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 274 275#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 276 277/* Offset for data I/O */ 278#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 279 280/* Offset for normal register accesses */ 281#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 282 283/* Offset for alternate registers */ 284#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 285 286/*----------------------------------------------------------------------- 287 * Debug Entry Mode 288 *----------------------------------------------------------------------- 289 * 290 */ 291#define CONFIG_SYS_DER 0 292 293#endif /* __CONFIG_H */ 294