1/* 2 * (C) Copyright 2000-2008 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8/* 9 * board/config.h - configuration options, board specific 10 */ 11 12#ifndef __CONFIG_H 13#define __CONFIG_H 14 15/* 16 * High Level Configuration Options 17 * (easy to change) 18 */ 19 20#define CONFIG_MPC855 1 /* This is a MPC855 CPU */ 21#define CONFIG_TQM855M 1 /* ...on a TQM8xxM module */ 22#define CONFIG_NSCU 1 23 24#define CONFIG_SYS_TEXT_BASE 0x40000000 25 26#define CONFIG_8xx_CONS_SCC1 1 /* Console is on SMC1 */ 27#define CONFIG_SYS_SMC_RXBUFLEN 128 28#define CONFIG_SYS_MAXIDLE 10 29 30#define CONFIG_66MHz 1 /* running at 66 MHz, 1:1 clock */ 31 32#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ 33 34#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 35 36#define CONFIG_BOARD_TYPES 1 /* support board types */ 37 38#define CONFIG_PREBOOT "echo;" \ 39 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 40 "echo" 41 42#undef CONFIG_BOOTARGS 43 44#define CONFIG_EXTRA_ENV_SETTINGS \ 45 "netdev=eth0\0" \ 46 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 47 "nfsroot=${serverip}:${rootpath}\0" \ 48 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 49 "addip=setenv bootargs ${bootargs} " \ 50 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 51 ":${hostname}:${netdev}:off panic=1\0" \ 52 "flash_nfs=run nfsargs addip;" \ 53 "bootm ${kernel_addr}\0" \ 54 "flash_self=run ramargs addip;" \ 55 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 56 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ 57 "rootpath=/opt/eldk/ppc_8xx\0" \ 58 "hostname=NSCU\0" \ 59 "bootfile=${hostname}/uImage\0" \ 60 "kernel_addr=40080000\0" \ 61 "ramdisk_addr=40180000\0" \ 62 "u-boot=${hostname}/u-image.bin\0" \ 63 "load=tftp 200000 ${u-boot}\0" \ 64 "update=prot off 40000000 +${filesize};" \ 65 "era 40000000 +${filesize};" \ 66 "cp.b 200000 40000000 ${filesize};" \ 67 "sete filesize;save\0" \ 68 "" 69#define CONFIG_BOOTCOMMAND "run flash_self" 70 71#define CONFIG_MISC_INIT_R 1 72 73#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 74#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 75 76#undef CONFIG_WATCHDOG /* watchdog disabled */ 77 78#define CONFIG_STATUS_LED 1 /* Status LED enabled */ 79 80#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ 81 82/* 83 * BOOTP options 84 */ 85#define CONFIG_BOOTP_SUBNETMASK 86#define CONFIG_BOOTP_GATEWAY 87#define CONFIG_BOOTP_HOSTNAME 88#define CONFIG_BOOTP_BOOTPATH 89#define CONFIG_BOOTP_BOOTFILESIZE 90 91 92#define CONFIG_MAC_PARTITION 93#define CONFIG_DOS_PARTITION 94 95#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ 96 97#define CONFIG_ISP1362_USB /* ISP1362 USB OTG controller */ 98 99 100/* 101 * Command line configuration. 102 */ 103#include <config_cmd_default.h> 104 105#define CONFIG_CMD_ASKENV 106#define CONFIG_CMD_DATE 107#define CONFIG_CMD_DHCP 108#define CONFIG_CMD_ELF 109#define CONFIG_CMD_IDE 110#define CONFIG_CMD_NFS 111#define CONFIG_CMD_SNTP 112 113 114#define CONFIG_NETCONSOLE 115 116 117/* 118 * Miscellaneous configurable options 119 */ 120#define CONFIG_SYS_LONGHELP /* undef to save memory */ 121#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 122 123#define CONFIG_CMDLINE_EDITING 1 /* add command line history 124*/ 125#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ 126 127#if defined(CONFIG_CMD_KGDB) 128#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 129#else 130#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 131#endif 132#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 133#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 134#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 135 136#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 137#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 138 139#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 140 141#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 142 143/* 144 * Low Level Configuration Settings 145 * (address mappings, register initial values, etc.) 146 * You should know what you are doing if you make changes here. 147 */ 148/*----------------------------------------------------------------------- 149 * Internal Memory Mapped Register 150 */ 151#define CONFIG_SYS_IMMR 0xFFF00000 152 153/*----------------------------------------------------------------------- 154 * Definitions for initial stack pointer and data area (in DPRAM) 155 */ 156#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 157#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ 158#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 159#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 160 161/*----------------------------------------------------------------------- 162 * Start addresses for the final memory configuration 163 * (Set up by the startup code) 164 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 165 */ 166#define CONFIG_SYS_SDRAM_BASE 0x00000000 167#define CONFIG_SYS_FLASH_BASE 0x40000000 168#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 169#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 170#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 171 172/* 173 * For booting Linux, the board info and command line data 174 * have to be in the first 8 MB of memory, since this is 175 * the maximum mapped by the Linux kernel during initialization. 176 */ 177#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 178 179/*----------------------------------------------------------------------- 180 * FLASH organization 181 */ 182 183/* use CFI flash driver */ 184#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ 185#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ 186#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size } 187#define CONFIG_SYS_FLASH_EMPTY_INFO 188#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 189#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 190#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ 191 192#define CONFIG_ENV_IS_IN_FLASH 1 193#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ 194#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ 195 196/* Address and size of Redundant Environment Sector */ 197#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) 198#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 199 200#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ 201 202/*----------------------------------------------------------------------- 203 * Hardware Information Block 204 */ 205#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ 206#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ 207#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ 208 209/*----------------------------------------------------------------------- 210 * Cache Configuration 211 */ 212#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 213#if defined(CONFIG_CMD_KGDB) 214#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 215#endif 216 217/*----------------------------------------------------------------------- 218 * SYPCR - System Protection Control 11-9 219 * SYPCR can only be written once after reset! 220 *----------------------------------------------------------------------- 221 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 222 */ 223#if defined(CONFIG_WATCHDOG) 224#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 225 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 226#else 227#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 228#endif 229 230/*----------------------------------------------------------------------- 231 * SIUMCR - SIU Module Configuration 11-6 232 *----------------------------------------------------------------------- 233 * PCMCIA config., multi-function pin tri-state 234 */ 235#ifndef CONFIG_CAN_DRIVER 236#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 237#else /* we must activate GPL5 in the SIUMCR for CAN */ 238#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 239#endif /* CONFIG_CAN_DRIVER */ 240 241/*----------------------------------------------------------------------- 242 * TBSCR - Time Base Status and Control 11-26 243 *----------------------------------------------------------------------- 244 * Clear Reference Interrupt Status, Timebase freezing enabled 245 */ 246#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 247 248/*----------------------------------------------------------------------- 249 * RTCSC - Real-Time Clock Status and Control Register 11-27 250 *----------------------------------------------------------------------- 251 */ 252#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 253 254/*----------------------------------------------------------------------- 255 * PISCR - Periodic Interrupt Status and Control 11-31 256 *----------------------------------------------------------------------- 257 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 258 */ 259#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 260 261/*----------------------------------------------------------------------- 262 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 263 *----------------------------------------------------------------------- 264 * Reset PLL lock status sticky bit, timer expired status bit and timer 265 * interrupt status bit 266 */ 267#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) 268 269/*----------------------------------------------------------------------- 270 * SCCR - System Clock and reset Control Register 15-27 271 *----------------------------------------------------------------------- 272 * Set clock output, timebase and RTC source and divider, 273 * power management and some other internal clocks 274 */ 275#define SCCR_MASK SCCR_EBDF11 276#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 277 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 278 SCCR_DFALCD00) 279 280/*----------------------------------------------------------------------- 281 * PCMCIA stuff 282 *----------------------------------------------------------------------- 283 * 284 */ 285/* NSCU use both slots, SLOT_A as "primary". */ 286#define CONFIG_PCMCIA_SLOT_A 1 287 288#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 289#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 290#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 291#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 292#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 293#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 294#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 295#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 296#define PCMCIA_MEM_WIN_NO 8 /* override default 4 in pcmcia.h */ 297#define PCMCIA_SOCKETS_NO 2 /* we have two sockets */ 298#undef NSCU_OE_INV /* PCMCIA_GCRX_CXOE was inverted on early boards */ 299 300/*----------------------------------------------------------------------- 301 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) 302 *----------------------------------------------------------------------- 303 */ 304 305#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ 306#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ 307 308#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 309#undef CONFIG_IDE_LED /* LED for ide not supported */ 310#undef CONFIG_IDE_RESET /* reset for ide not supported */ 311 312#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE buses */ 313#define CONFIG_SYS_IDE_MAXDEVICE 4 /* max. 2 drives per IDE bus */ 314 315#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 316#define CONFIG_SYS_ATA_IDE1_OFFSET (4 * CONFIG_SYS_PCMCIA_MEM_SIZE) /* starts @ 4th window */ 317 318#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 319 320/* Offset for data I/O */ 321#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 322 323/* Offset for normal register accesses */ 324#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 325 326/* Offset for alternate registers */ 327#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 328 329/*----------------------------------------------------------------------- 330 * 331 *----------------------------------------------------------------------- 332 * 333 */ 334#define CONFIG_SYS_DER 0 335 336/* 337 * Init Memory Controller: 338 * 339 * BR0/1 and OR0/1 (FLASH) 340 */ 341 342#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 343#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ 344 345/* used to re-map FLASH both when starting from SRAM or FLASH: 346 * restrict access enough to keep SRAM working (if any) 347 * but not too much to meddle with FLASH accesses 348 */ 349#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 350#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 351 352/* 353 * FLASH timing: 354 */ 355#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ 356 OR_SCY_3_CLK | OR_EHTR | OR_BI) 357 358#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 359#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 360#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) 361 362#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP 363#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 364#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) 365 366/* 367 * BR2/3 and OR2/3 (SDRAM) 368 * 369 */ 370#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ 371#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ 372#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ 373 374/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 375#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 376 377#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) 378#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 379 380#ifndef CONFIG_CAN_DRIVER 381#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 382#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 383#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ 384#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ 385#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ 386#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) 387#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ 388 BR_PS_8 | BR_MS_UPMB | BR_V ) 389#endif /* CONFIG_CAN_DRIVER */ 390 391#ifdef CONFIG_ISP1362_USB 392#define CONFIG_SYS_ISP1362_BASE 0xD0000000 /* ISP1362 mapped at 0xD0000000 */ 393#define CONFIG_SYS_ISP1362_OR_AM 0xFFFF8000 /* 32 kB address mask */ 394#define CONFIG_SYS_OR5_ISP1362 (CONFIG_SYS_ISP1362_OR_AM | OR_CSNT_SAM | \ 395 OR_ACS_DIV2 | OR_BI | OR_SCY_5_CLK) 396#define CONFIG_SYS_BR5_ISP1362 ((CONFIG_SYS_ISP1362_BASE & BR_BA_MSK) | \ 397 BR_PS_16 | BR_MS_GPCM | BR_V ) 398#endif /* CONFIG_ISP1362_USB */ 399 400/* 401 * Memory Periodic Timer Prescaler 402 * 403 * The Divider for PTA (refresh timer) configuration is based on an 404 * example SDRAM configuration (64 MBit, one bank). The adjustment to 405 * the number of chip selects (NCS) and the actually needed refresh 406 * rate is done by setting MPTPR. 407 * 408 * PTA is calculated from 409 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) 410 * 411 * gclk CPU clock (not bus clock!) 412 * Trefresh Refresh cycle * 4 (four word bursts used) 413 * 414 * 4096 Rows from SDRAM example configuration 415 * 1000 factor s -> ms 416 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration 417 * 4 Number of refresh cycles per period 418 * 64 Refresh cycle in ms per number of rows 419 * -------------------------------------------- 420 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 421 * 422 * 50 MHz => 50.000.000 / Divider = 98 423 * 66 Mhz => 66.000.000 / Divider = 129 424 * 80 Mhz => 80.000.000 / Divider = 156 425 */ 426 427#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) 428#define CONFIG_SYS_MAMR_PTA 98 429 430/* 431 * For 16 MBit, refresh rates could be 31.3 us 432 * (= 64 ms / 2K = 125 / quad bursts). 433 * For a simpler initialization, 15.6 us is used instead. 434 * 435 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks 436 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank 437 */ 438#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ 439#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ 440 441/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ 442#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ 443#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ 444 445/* 446 * MAMR settings for SDRAM 447 */ 448 449/* 8 column SDRAM */ 450#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 451 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 452 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 453/* 9 column SDRAM */ 454#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 455 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 456 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 457 458#undef CONFIG_SCC1_ENET 459#define CONFIG_FEC_ENET 460 461/* pass open firmware flat tree */ 462#define CONFIG_OF_LIBFDT 1 463#define CONFIG_OF_BOARD_SETUP 1 464#define CONFIG_HWCONFIG 1 465 466#endif /* __CONFIG_H */ 467