LXR uboot/include/configs/eb

   1/*
   2 * (C) Copyright 2008-2009
   3 * BuS Elektronik GmbH & Co. KG <www.bus-elektronik.de>
   4 * Jens Scharsig <esw@bus-elektronik.de>
   5 *
   6 * Configuation settings for the EB+CPUx9K2 board.
   7 *
   8 * SPDX-License-Identifier:     GPL-2.0+
   9 */
  10
  11#ifndef _CONFIG_EB_CPUx9K2_H_
  12#define _CONFIG_EB_CPUx9K2_H_
  13
  14/*--------------------------------------------------------------------------*/
  15
  16#define CONFIG_AT91RM9200               /* It's an Atmel AT91RM9200 SoC */
  17#define CONFIG_EB_CPUX9K2               /* on an EP+CPUX9K2 Board       */
  18#define USE_920T_MMU
  19
  20#define CONFIG_VERSION_VARIABLE
  21#define CONFIG_IDENT_STRING     " on EB+CPUx9K2"
  22
  23#include <asm/hardware.h>       /* needed for port definitions */
  24
  25#define CONFIG_MISC_INIT_R
  26#define CONFIG_BOARD_EARLY_INIT_F
  27
  28#define MACH_TYPE_EB_CPUX9K2            1977
  29#define CONFIG_MACH_TYPE                MACH_TYPE_EB_CPUX9K2
  30
  31#define CONFIG_SYS_CACHELINE_SIZE       32
  32#define CONFIG_SYS_DCACHE_OFF
  33
  34/*--------------------------------------------------------------------------*/
  35#ifndef CONFIG_RAMBOOT
  36#define CONFIG_SYS_TEXT_BASE            0x00000000
  37#else
  38#define CONFIG_SKIP_LOWLEVEL_INIT
  39#define CONFIG_SYS_TEXT_BASE            0x21f00000
  40#endif
  41#define CONFIG_SYS_LOAD_ADDR            0x21000000  /* default load address */
  42#define CONFIG_STANDALONE_LOAD_ADDR     0x21000000
  43
  44#define CONFIG_SYS_BOOT_SIZE            0x00 /* 0 KBytes */
  45#define CONFIG_SYS_U_BOOT_BASE          PHYS_FLASH_1
  46#define CONFIG_SYS_U_BOOT_SIZE          0x60000 /* 384 KBytes */
  47
  48#define CONFIG_BOOT_RETRY_TIME          30
  49#define CONFIG_CMDLINE_EDITING
  50
  51#define CONFIG_SYS_PROMPT       "U-Boot> "      /* Monitor Command Prompt */
  52#define CONFIG_SYS_CBSIZE       512             /* Console I/O Buffer Size */
  53#define CONFIG_SYS_MAXARGS      32              /* max number of command args */
  54#define CONFIG_SYS_PBSIZE       \
  55        (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  56
  57/*
  58 * ARM asynchronous clock
  59 */
  60
  61#define AT91C_MAIN_CLOCK        179404800       /* from 12.288 MHz * 73 / 5 */
  62#define AT91C_MASTER_CLOCK      (AT91C_MAIN_CLOCK / 3)
  63#define CONFIG_SYS_HZ           1000
  64#define CONFIG_SYS_HZ_CLOCK     (AT91C_MASTER_CLOCK / 2)
  65
  66#define CONFIG_SYS_AT91_SLOW_CLOCK      32768           /* slow clock */
  67
  68#define CONFIG_CMDLINE_TAG              1
  69#define CONFIG_SETUP_MEMORY_TAGS        1
  70#define CONFIG_INITRD_TAG               1
  71
  72#define CONFIG_SYS_USE_MAIN_OSCILLATOR  1
  73/* flash */
  74#define CONFIG_SYS_EBI_CFGR_VAL         0x00000000
  75#define CONFIG_SYS_SMC_CSR0_VAL         0x00003284 /* 16bit, 2 TDF, 4 WS */
  76
  77/* clocks */
  78#define CONFIG_SYS_PLLAR_VAL            0x20483E05 /* 179.4048 MHz for PCK */
  79#define CONFIG_SYS_PLLBR_VAL            0x104C3E0A /* 47.3088 MHz (for USB) */
  80#define CONFIG_SYS_MCKR_VAL             0x00000202 /* PCK/3 = MCK Clock */
  81
  82/*
  83 * Size of malloc() pool
  84 */
  85
  86#define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
  87
  88/*
  89 * sdram
  90 */
  91
  92#define CONFIG_NR_DRAM_BANKS            1
  93
  94#define CONFIG_SYS_SDRAM_BASE           0x20000000
  95#define CONFIG_SYS_SDRAM_SIZE           0x04000000  /* 64 megs */
  96#define CONFIG_SYS_INIT_SP_ADDR         0x00204000  /* use internal SRAM */
  97
  98#define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE
  99#define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_MEMTEST_START + \
 100                                        CONFIG_SYS_SDRAM_SIZE - 0x00400000 - \
 101                                        CONFIG_SYS_MALLOC_LEN)
 102
 103#define CONFIG_SYS_PIOC_ASR_VAL         0xFFFF0000 /* PIOC as D16/D31 */
 104#define CONFIG_SYS_PIOC_BSR_VAL         0x00000000
 105#define CONFIG_SYS_PIOC_PDR_VAL         0xFFFF0000
 106#define CONFIG_SYS_EBI_CSA_VAL          0x00000002 /* CS1=SDRAM */
 107#define CONFIG_SYS_SDRC_CR_VAL          0x2188c159 /* set up the SDRAM */
 108#define CONFIG_SYS_SDRAM                0x20000000 /* address of the SDRAM */
 109#define CONFIG_SYS_SDRAM1               0x20000080 /* address of the SDRAM */
 110#define CONFIG_SYS_SDRAM_VAL            0x00000000 /* value written to SDRAM */
 111#define CONFIG_SYS_SDRC_MR_VAL          0x00000002 /* Precharge All */
 112#define CONFIG_SYS_SDRC_MR_VAL1         0x00000004 /* refresh */
 113#define CONFIG_SYS_SDRC_MR_VAL2         0x00000003 /* Load Mode Register */
 114#define CONFIG_SYS_SDRC_MR_VAL3         0x00000000 /* Normal Mode */
 115#define CONFIG_SYS_SDRC_TR_VAL          0x000002E0 /* Write refresh rate */
 116
 117/*
 118 * Command line configuration
 119 */
 120
 121#include <config_cmd_default.h>
 122
 123#define CONFIG_CMD_BMP
 124#define CONFIG_CMD_DATE
 125#define CONFIG_CMD_DHCP
 126#define CONFIG_CMD_I2C
 127#define CONFIG_CMD_MII
 128#define CONFIG_CMD_NAND
 129#define CONFIG_CMD_PING
 130#define CONFIG_I2C_CMD_TREE
 131#define CONFIG_CMD_USB
 132#define CONFIG_CMD_FAT
 133#define CONFIG_CMD_UBI
 134#define CONFIG_CMD_MTDPARTS
 135#define CONFIG_CMD_UBIFS
 136#define CONFIG_SYS_LONGHELP
 137
 138/*
 139 * MTD defines
 140 */
 141
 142#define CONFIG_FLASH_CFI_MTD
 143#define CONFIG_MTD_DEVICE
 144#define CONFIG_MTD_PARTITIONS
 145#define CONFIG_RBTREE
 146#define CONFIG_LZO
 147
 148#define MTDIDS_DEFAULT          "nor0=physmap-flash.0,nand0=atmel_nand"
 149#define MTDPARTS_DEFAULT        "mtdparts="                             \
 150                                        "physmap-flash.0:"              \
 151                                                "512k(U-Boot),"         \
 152                                                "128k(Env),"            \
 153                                                "128k(Splash),"         \
 154                                                "4M(Kernel),"           \
 155                                                "384k(MiniFS),"         \
 156                                                "-(FS)"                 \
 157                                        ";"                             \
 158                                        "atmel_nand:"                   \
 159                                                "1M(emergency),"        \
 160                                                "-(data)"
 161/*
 162 * Hardware drivers
 163 */
 164#define CONFIG_USB_ATMEL
 165#define CONFIG_USB_OHCI_NEW
 166#define CONFIG_AT91C_PQFP_UHPBUG
 167#define CONFIG_USB_STORAGE
 168#define CONFIG_DOS_PARTITION
 169#define CONFIG_ISO_PARTITION
 170#define CONFIG_EFI_PARTITION
 171
 172#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      1
 173#define CONFIG_SYS_USB_OHCI_CPU_INIT
 174#define CONFIG_SYS_USB_OHCI_REGS_BASE           0x00300000
 175#define CONFIG_SYS_USB_OHCI_SLOT_NAME           "at91rm9200"
 176
 177/*
 178 * UART/CONSOLE
 179 */
 180
 181#define CONFIG_BAUDRATE 115200
 182#define CONFIG_ATMEL_USART
 183#define CONFIG_USART_BASE       ATMEL_BASE_DBGU
 184#define CONFIG_USART_ID         0/* ignored in arm */
 185
 186/*
 187 * network
 188 */
 189
 190#define CONFIG_NET_RETRY_COUNT          10
 191#define CONFIG_RESET_PHY_R              1
 192
 193#define CONFIG_DRIVER_AT91EMAC          1
 194#define CONFIG_DRIVER_AT91EMAC_QUIET    1
 195#define CONFIG_SYS_RX_ETH_BUFFER        8
 196#define CONFIG_MII                      1
 197
 198/*
 199 * BOOTP options
 200 */
 201#define CONFIG_BOOTP_BOOTFILESIZE
 202#define CONFIG_BOOTP_BOOTPATH
 203#define CONFIG_BOOTP_GATEWAY
 204#define CONFIG_BOOTP_HOSTNAME
 205
 206/*
 207 * I2C-Bus
 208 */
 209
 210#define CONFIG_SYS_I2C
 211#define CONFIG_SYS_I2C_SOFT             /* I2C bit-banged */
 212#define CONFIG_SYS_I2C_SOFT_SPEED       50000
 213#define CONFIG_SYS_I2C_SOFT_SLAVE       0
 214
 215/* Software  I2C driver configuration */
 216
 217#define AT91_PIN_SDA                    (1<<25)         /* AT91C_PIO_PA25 */
 218#define AT91_PIN_SCL                    (1<<26)         /* AT91C_PIO_PA26 */
 219
 220#define CONFIG_SYS_I2C_INIT_BOARD
 221
 222#define I2C_INIT        i2c_init_board();
 223#define I2C_ACTIVE      writel(ATMEL_PMX_AA_TWD, &pio->pioa.mddr);
 224#define I2C_TRISTATE    writel(ATMEL_PMX_AA_TWD, &pio->pioa.mder);
 225#define I2C_READ        ((readl(&pio->pioa.pdsr) & ATMEL_PMX_AA_TWD) != 0)
 226#define I2C_SDA(bit)                                            \
 227        if (bit)                                                \
 228                writel(ATMEL_PMX_AA_TWD, &pio->pioa.sodr);      \
 229        else                                                    \
 230                writel(ATMEL_PMX_AA_TWD, &pio->pioa.codr);
 231#define I2C_SCL(bit)                                            \
 232        if (bit)                                                \
 233                writel(ATMEL_PMX_AA_TWCK, &pio->pioa.sodr);     \
 234        else                                                    \
 235                writel(ATMEL_PMX_AA_TWCK, &pio->pioa.codr);
 236
 237#define I2C_DELAY       udelay(2500000/CONFIG_SYS_I2C_SOFT_SPEED)
 238
 239/* I2C-RTC */
 240
 241#ifdef CONFIG_CMD_DATE
 242#define CONFIG_RTC_DS1338
 243#define CONFIG_SYS_I2C_RTC_ADDR 0x68
 244#endif
 245
 246/* EEPROM */
 247
 248#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
 249#define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 250
 251/* FLASH organization */
 252
 253/*  NOR-FLASH */
 254#define CONFIG_FLASH_SHOW_PROGRESS      45
 255
 256#define CONFIG_FLASH_CFI_DRIVER 1
 257
 258#define PHYS_FLASH_1                    0x10000000
 259#define PHYS_FLASH_SIZE                 0x01000000  /* 16 megs main flash */
 260#define CONFIG_SYS_FLASH_CFI            1
 261#define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 262
 263#define CONFIG_SYS_FLASH_PROTECTION     1
 264#define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 265#define CONFIG_SYS_MAX_FLASH_BANKS      1
 266#define CONFIG_SYS_MAX_FLASH_SECT       512
 267#define CONFIG_SYS_FLASH_ERASE_TOUT     6000
 268#define CONFIG_SYS_FLASH_WRITE_TOUT     2000
 269
 270/* NAND */
 271
 272#define CONFIG_SYS_MAX_NAND_DEVICE      1
 273#define CONFIG_SYS_NAND_BASE            0x40000000
 274#define CONFIG_SYS_NAND_DBW_8           1
 275
 276/* Status LED's */
 277
 278#define CONFIG_STATUS_LED               1
 279#define CONFIG_BOARD_SPECIFIC_LED       1
 280
 281#define STATUS_LED_BOOT                 1
 282#define STATUS_LED_ACTIVE               0
 283
 284#define STATUS_LED_BIT                  1       /* AT91C_PIO_PD0 green LED */
 285#define STATUS_LED_PERIOD               (CONFIG_SYS_HZ / 2)
 286#define STATUS_LED_STATE                STATUS_LED_OFF          /* BLINKING */
 287#define STATUS_LED_BIT1                 2       /* AT91C_PIO_PD1  red LED */
 288#define STATUS_LED_STATE1               STATUS_LED_ON           /* BLINKING */
 289#define STATUS_LED_PERIOD1              (CONFIG_SYS_HZ / 4)
 290
 291#define CONFIG_VIDEO                    1
 292
 293/* Options */
 294
 295#ifdef CONFIG_VIDEO
 296
 297#define CONFIG_VIDEO_VCXK                       1
 298
 299#define CONFIG_SPLASH_SCREEN                    1
 300
 301#define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN       4
 302#define CONFIG_SYS_VCXK_BASE    0x30000000
 303
 304#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN         (1<<3)
 305#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT        piob
 306#define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR         odr
 307
 308#define CONFIG_SYS_VCXK_ENABLE_PIN              (1<<5)
 309#define CONFIG_SYS_VCXK_ENABLE_PORT             piob
 310#define CONFIG_SYS_VCXK_ENABLE_DDR              oer
 311
 312#define CONFIG_SYS_VCXK_REQUEST_PIN             (1<<2)
 313#define CONFIG_SYS_VCXK_REQUEST_PORT            piob
 314#define CONFIG_SYS_VCXK_REQUEST_DDR             oer
 315
 316#define CONFIG_SYS_VCXK_INVERT_PIN              (1<<4)
 317#define CONFIG_SYS_VCXK_INVERT_PORT             piob
 318#define CONFIG_SYS_VCXK_INVERT_DDR              oer
 319
 320#define CONFIG_SYS_VCXK_RESET_PIN               (1<<6)
 321#define CONFIG_SYS_VCXK_RESET_PORT              piob
 322#define CONFIG_SYS_VCXK_RESET_DDR               oer
 323
 324#endif  /* CONFIG_VIDEO */
 325
 326/* Environment */
 327
 328#define CONFIG_BOOTDELAY                5
 329
 330#define CONFIG_ENV_IS_IN_FLASH          1
 331#define CONFIG_ENV_ADDR                 (PHYS_FLASH_1 + 0x80000)
 332#define CONFIG_ENV_SIZE                 0x20000 /* sectors are 128K here */
 333
 334#define CONFIG_BAUDRATE                 115200
 335
 336#define CONFIG_BOOTCOMMAND              "run nfsboot"
 337
 338#define CONFIG_NFSBOOTCOMMAND                                           \
 339                "dhcp $(copy_addr) uImage_cpux9k2;"                     \
 340                "run bootargsdefaults;"                                 \
 341                "set bootargs $(bootargs) boot=nfs "                    \
 342                ";echo $(bootargs)"                                     \
 343        ";bootm"
 344
 345#define CONFIG_EXTRA_ENV_SETTINGS                                       \
 346        "displaywidth=256\0"                                            \
 347        "displayheight=512\0"                                           \
 348        "displaybsteps=1023\0"                                          \
 349        "ubootaddr=10000000\0"                                          \
 350        "splashimage=100A0000\0"                                        \
 351        "kerneladdr=100C0000\0"                                         \
 352        "kernelsize=00400000\0"                                         \
 353        "rootfsaddr=10520000\0"                                         \
 354        "copy_addr=21200000\0"                                          \
 355        "rootfssize=00AE0000\0"                                         \
 356        "mtdids=" MTDIDS_DEFAULT "\0"                                   \
 357        "mtdparts=" MTDPARTS_DEFAULT "\0"                               \
 358        "bootargsdefaults=set bootargs "                                \
 359                "console=ttyS0,115200 "                                 \
 360                "video=vcxk_fb:xres:${displaywidth},"                   \
 361                        "yres:${displayheight},"                        \
 362                        "bres:${displaybsteps} "                        \
 363                "mem=62M "                                              \
 364                "panic=10 "                                             \
 365                "uboot=\\\"${ver}\\\" "                                 \
 366                "\0"                                                    \
 367        "update_kernel=protect off $(kerneladdr) +$(kernelsize);"       \
 368                "dhcp $(copy_addr) uImage_cpux9k2;"                     \
 369                "erase $(kerneladdr) +$(kernelsize);"                   \
 370                "cp.b $(fileaddr) $(kerneladdr) $(filesize);"           \
 371                "protect on $(kerneladdr) +$(kernelsize)"               \
 372                "\0"                                                    \
 373        "update_root=protect off $(rootfsaddr) +$(rootfssize);"         \
 374                "dhcp $(copy_addr) rfs;"                                \
 375                "erase $(rootfsaddr) +$(rootfssize);"                   \
 376                "cp.b $(fileaddr) $(rootfsaddr) $(filesize);"           \
 377                "\0"                                                    \
 378        "update_uboot=protect off 10000000 1007FFFF;"                   \
 379                "dhcp $(copy_addr) u-boot_eb_cpux9k2;"                  \
 380                "erase 10000000 1007FFFF;"                              \
 381                "cp.b $(fileaddr) $(ubootaddr) $(filesize);"            \
 382                "protect on 10000000 1007FFFF;reset\0"                  \
 383        "update_splash=protect off $(splashimage) +20000;"              \
 384                "dhcp $(copy_addr) splash_eb_cpux9k2.bmp;"              \
 385                "erase $(splashimage) +20000;"                          \
 386                "cp.b $(fileaddr) $(splashimage) $(filesize);"          \
 387                "protect on $(splashimage) +20000;reset\0"              \
 388        "emergency=run bootargsdefaults;"                               \
 389                "set bootargs $(bootargs) root=initramfs boot=emergency " \
 390                ";bootm $(kerneladdr)\0"                                \
 391        "netemergency=run bootargsdefaults;"                            \
 392                "dhcp $(copy_addr) uImage_cpux9k2;"                     \
 393                "set bootargs $(bootargs) root=initramfs boot=emergency " \
 394                ";bootm $(copy_addr)\0"                                 \
 395        "norboot=run bootargsdefaults;"                                 \
 396                "set bootargs $(bootargs) root=initramfs boot=local "   \
 397                ";bootm $(kerneladdr)\0"                                \
 398        "nandboot=run bootargsdefaults;"                                \
 399                "set bootargs $(bootargs) root=initramfs boot=nand "    \
 400                ";bootm $(kerneladdr)\0"                                \
 401        " "
 402
 403/*--------------------------------------------------------------------------*/
 404
 405#endif
 406
 407/* EOF */
 408