1/* 2 * (C) Copyright 2000 3 * Murray Jensen <Murray.Jensen@cmst.csiro.au> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8/* 9 * Config header file for Hymod board 10 */ 11 12#ifndef __CONFIG_H 13#define __CONFIG_H 14 15/* 16 * High Level Configuration Options 17 * (easy to change) 18 */ 19 20#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ 21#define CONFIG_HYMOD 1 /* ...on a Hymod board */ 22#define CONFIG_CPM2 1 /* Has a CPM2 */ 23 24#define CONFIG_SYS_TEXT_BASE 0x40000000 25 26#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ 27 28#define CONFIG_BOARD_POSTCLK_INIT /* have board_postclk_init() function */ 29 30/* 31 * select serial console configuration 32 * 33 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then 34 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 35 * for SCC). 36 * 37 * if CONFIG_CONS_NONE is defined, then the serial console routines must 38 * defined elsewhere (for example, on the cogent platform, there are serial 39 * ports on the motherboard which are used for the serial console - see 40 * cogent/cma101/serial.[ch]). 41 */ 42#undef CONFIG_CONS_ON_SMC /* define if console on SMC */ 43#define CONFIG_CONS_ON_SCC /* define if console on SCC */ 44#undef CONFIG_CONS_NONE /* define if console on something else*/ 45#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ 46#define CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ 47#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */ 48#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/ 49 50/* 51 * select ethernet configuration 52 * 53 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then 54 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 55 * for FCC) 56 * 57 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be 58 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. 59 */ 60#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ 61#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ 62#undef CONFIG_ETHER_NONE /* define if ether on something else */ 63#define CONFIG_ETHER_INDEX 1 /* which channel for ether */ 64#define CONFIG_ETHER_LOOPBACK_TEST /* add ether external loopback test */ 65 66#ifdef CONFIG_ETHER_ON_FCC 67 68#if (CONFIG_ETHER_INDEX == 1) 69 70/* 71 * - Rx-CLK is CLK10 72 * - Tx-CLK is CLK11 73 * - RAM for BD/Buffers is on the 60x Bus (see 28-13) 74 * - Enable Full Duplex in FSMR 75 */ 76# define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) 77# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK11) 78# define CONFIG_SYS_CPMFCR_RAMTYPE 0 79# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) 80 81# define MDIO_PORT 0 /* Port A */ 82# define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ 83 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) 84# define MDC_DECLARE MDIO_DECLARE 85 86# define MDIO_DATA_PINMASK 0x00040000 /* Pin 13 */ 87# define MDIO_CLCK_PINMASK 0x00080000 /* Pin 12 */ 88 89#elif (CONFIG_ETHER_INDEX == 2) 90 91/* 92 * - Rx-CLK is CLK13 93 * - Tx-CLK is CLK14 94 * - RAM for BD/Buffers is on the 60x Bus (see 28-13) 95 * - Enable Full Duplex in FSMR 96 */ 97# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) 98# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) 99# define CONFIG_SYS_CPMFCR_RAMTYPE 0 100# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) 101 102# define MDIO_PORT 0 /* Port A */ 103# define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ 104 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) 105# define MDC_DECLARE MDIO_DECLARE 106 107# define MDIO_DATA_PINMASK 0x00000040 /* Pin 25 */ 108# define MDIO_CLCK_PINMASK 0x00000080 /* Pin 24 */ 109 110#elif (CONFIG_ETHER_INDEX == 3) 111 112/* 113 * - Rx-CLK is CLK15 114 * - Tx-CLK is CLK16 115 * - RAM for BD/Buffers is on the 60x Bus (see 28-13) 116 * - Enable Full Duplex in FSMR 117 */ 118# define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK) 119# define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16) 120# define CONFIG_SYS_CPMFCR_RAMTYPE 0 121# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) 122 123# define MDIO_PORT 0 /* Port A */ 124# define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ 125 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) 126# define MDC_DECLARE MDIO_DECLARE 127 128# define MDIO_DATA_PINMASK 0x00000100 /* Pin 23 */ 129# define MDIO_CLCK_PINMASK 0x00000200 /* Pin 22 */ 130 131#endif /* CONFIG_ETHER_INDEX */ 132 133#define CONFIG_MII /* MII PHY management */ 134#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ 135 136#define MDIO_ACTIVE (iop->pdir |= MDIO_DATA_PINMASK) 137#define MDIO_TRISTATE (iop->pdir &= ~MDIO_DATA_PINMASK) 138#define MDIO_READ ((iop->pdat & MDIO_DATA_PINMASK) != 0) 139 140#define MDIO(bit) if(bit) iop->pdat |= MDIO_DATA_PINMASK; \ 141 else iop->pdat &= ~MDIO_DATA_PINMASK 142 143#define MDC(bit) if(bit) iop->pdat |= MDIO_CLCK_PINMASK; \ 144 else iop->pdat &= ~MDIO_CLCK_PINMASK 145 146#define MIIDELAY udelay(1) 147 148#endif /* CONFIG_ETHER_ON_FCC */ 149 150 151/* other options */ 152#define CONFIG_HARD_I2C 1 /* To enable I2C hardware support */ 153#define CONFIG_DTT_ADM1021 1 /* ADM1021 temp sensor support */ 154 155/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ 156#ifdef DEBUG 157#define CONFIG_8260_CLKIN 33333333 /* in Hz */ 158#else 159#define CONFIG_8260_CLKIN 66666666 /* in Hz */ 160#endif 161 162#if defined(CONFIG_CONS_USE_EXTC) 163#define CONFIG_BAUDRATE 115200 164#else 165#define CONFIG_BAUDRATE 9600 166#endif 167 168/* default ip addresses - these will be overridden */ 169#define CONFIG_IPADDR 192.168.1.1 /* hymod "boot" address */ 170#define CONFIG_SERVERIP 192.168.1.254 /* hymod "server" address */ 171 172#define CONFIG_LAST_STAGE_INIT 173 174/* 175 * BOOTP options 176 */ 177#define CONFIG_BOOTP_BOOTFILESIZE 178#define CONFIG_BOOTP_BOOTPATH 179#define CONFIG_BOOTP_GATEWAY 180#define CONFIG_BOOTP_HOSTNAME 181 182 183/* 184 * Command line configuration. 185 */ 186#include <config_cmd_default.h> 187 188#define CONFIG_CMD_ASKENV 189#define CONFIG_CMD_BSP 190#define CONFIG_CMD_CACHE 191#define CONFIG_CMD_CDP 192#define CONFIG_CMD_DATE 193#define CONFIG_CMD_DHCP 194#define CONFIG_CMD_DIAG 195#define CONFIG_CMD_DTT 196#define CONFIG_CMD_EEPROM 197#define CONFIG_CMD_ELF 198#define CONFIG_CMD_FAT 199#define CONFIG_CMD_I2C 200#define CONFIG_CMD_IMMAP 201#define CONFIG_CMD_IRQ 202#define CONFIG_CMD_KGDB 203#define CONFIG_CMD_MII 204#define CONFIG_CMD_PING 205#define CONFIG_CMD_PORTIO 206#define CONFIG_CMD_REGINFO 207#define CONFIG_CMD_SAVES 208#define CONFIG_CMD_SDRAM 209#define CONFIG_CMD_SNTP 210 211#undef CONFIG_CMD_FPGA 212#undef CONFIG_CMD_XIMG 213 214#ifdef DEBUG 215#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ 216#else 217#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 218#define CONFIG_BOOT_RETRY_TIME 30 /* retry autoboot after 30 secs */ 219#define CONFIG_BOOT_RETRY_MIN 1 /* can go down to 1 second timeout */ 220/* Be selective on what keys can delay or stop the autoboot process 221 * To stop use: " " 222 */ 223#define CONFIG_AUTOBOOT_KEYED 224#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, " \ 225 "press <SPACE> to stop\n", bootdelay 226#define CONFIG_AUTOBOOT_STOP_STR " " 227#undef CONFIG_AUTOBOOT_DELAY_STR 228#define DEBUG_BOOTKEYS 0 229#endif 230 231#if defined(CONFIG_CMD_KGDB) 232#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ 233#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ 234#undef CONFIG_KGDB_NONE /* define if kgdb on something else */ 235#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */ 236#define CONFIG_KGDB_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ 237#define CONFIG_KGDB_EXTC_RATE 3686400 /* serial ext clk rate in Hz */ 238#define CONFIG_KGDB_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/ 239# if defined(CONFIG_KGDB_USE_EXTC) 240#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ 241# else 242#define CONFIG_KGDB_BAUDRATE 9600 /* speed to run kgdb serial port at */ 243# endif 244#endif 245 246#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ 247 248#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */ 249 250/* 251 * Hymod specific configurable options 252 */ 253#undef CONFIG_SYS_HYMOD_DBLEDS /* walk mezz board LEDs */ 254 255/* 256 * Miscellaneous configurable options 257 */ 258#define CONFIG_SYS_LONGHELP /* undef to save memory */ 259#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 260#if defined(CONFIG_CMD_KGDB) 261#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 262#else 263#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 264#endif 265#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 266#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 267#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 268 269#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ 270#define CONFIG_SYS_MEMTEST_END 0x03c00000 /* 4 ... 60 MB in DRAM */ 271 272#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 273 274#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 275 276#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } 277 278#define CONFIG_SYS_I2C_SPEED 50000 279#define CONFIG_SYS_I2C_SLAVE 0x7e 280 281/* these are for the ST M24C02 2kbit serial i2c eeprom */ 282#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */ 283#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ 284/* mask of address bits that overflow into the "EEPROM chip address" */ 285#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 286 287#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16 byte write page size */ 288#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ 289 290#define CONFIG_SYS_I2C_MULTI_EEPROMS 1 /* hymod has two eeproms */ 291 292#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* philips PCF8563 RTC address */ 293 294/* 295 * standard dtt sensor configuration - bottom bit will determine local or 296 * remote sensor of the ADM1021, the rest determines index into 297 * CONFIG_SYS_DTT_ADM1021 array below. 298 * 299 * On HYMOD board, the remote sensor should be connected to the MPC8260 300 * temperature diode thingy, but an errata said this didn't work and 301 * should be disabled - so it isn't connected. 302 */ 303#if 0 304#define CONFIG_DTT_SENSORS { 0, 1 } 305#else 306#define CONFIG_DTT_SENSORS { 0 } 307#endif 308 309/* 310 * ADM1021 temp sensor configuration (see dtt/adm1021.c for details). 311 * there will be one entry in this array for each two (dummy) sensors in 312 * CONFIG_DTT_SENSORS. 313 * 314 * For HYMOD board: 315 * - only one ADM1021 316 * - i2c addr 0x2a (both ADD0 and ADD1 are N/C) 317 * - conversion rate 0x02 = 0.25 conversions/second 318 * - ALERT ouput disabled 319 * - local temp sensor enabled, min set to 0 deg, max set to 85 deg 320 * - remote temp sensor disabled (see comment for CONFIG_DTT_SENSORS above) 321 */ 322#define CONFIG_SYS_DTT_ADM1021 { { 0x2a, 0x02, 0, 1, 0, 85, 0, } } 323 324/* 325 * Low Level Configuration Settings 326 * (address mappings, register initial values, etc.) 327 * You should know what you are doing if you make changes here. 328 */ 329 330/*----------------------------------------------------------------------- 331 * Hard Reset Configuration Words 332 * 333 * if you change bits in the HRCW, you must also change the CONFIG_SYS_* 334 * defines for the various registers affected by the HRCW e.g. changing 335 * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. 336 */ 337#ifdef DEBUG 338#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\ 339 HRCW_ISB100|HRCW_BMS|HRCW_MMR11|HRCW_APPC10|\ 340 HRCW_MODCK_H0010) 341#else 342#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\ 343 HRCW_ISB100|HRCW_BMS|HRCW_MMR11|HRCW_APPC10|\ 344 HRCW_MODCK_H0101) 345#endif 346/* no slaves so just duplicate the master hrcw */ 347#define CONFIG_SYS_HRCW_SLAVE1 CONFIG_SYS_HRCW_MASTER 348#define CONFIG_SYS_HRCW_SLAVE2 CONFIG_SYS_HRCW_MASTER 349#define CONFIG_SYS_HRCW_SLAVE3 CONFIG_SYS_HRCW_MASTER 350#define CONFIG_SYS_HRCW_SLAVE4 CONFIG_SYS_HRCW_MASTER 351#define CONFIG_SYS_HRCW_SLAVE5 CONFIG_SYS_HRCW_MASTER 352#define CONFIG_SYS_HRCW_SLAVE6 CONFIG_SYS_HRCW_MASTER 353#define CONFIG_SYS_HRCW_SLAVE7 CONFIG_SYS_HRCW_MASTER 354 355/*----------------------------------------------------------------------- 356 * Internal Memory Mapped Register 357 */ 358#define CONFIG_SYS_IMMR 0xF0000000 359 360/*----------------------------------------------------------------------- 361 * Definitions for initial stack pointer and data area (in DPRAM) 362 */ 363#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 364#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ 365#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 366#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 367 368/*----------------------------------------------------------------------- 369 * Start addresses for the final memory configuration 370 * (Set up by the startup code) 371 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 372 */ 373#define CONFIG_SYS_SDRAM_BASE 0x00000000 374#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE 375#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 376#define CONFIG_SYS_FPGA_BASE 0x80000000 377/* 378 * unfortunately, CONFIG_SYS_MONITOR_LEN must include the 379 * (very large i.e. 256kB) environment flash sector 380 */ 381#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor*/ 382#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ 383 384/* 385 * For booting Linux, the board info and command line data 386 * have to be in the first 8 MB of memory, since this is 387 * the maximum mapped by the Linux kernel during initialization. 388 */ 389#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/ 390 391/*----------------------------------------------------------------------- 392 * FLASH organization 393 */ 394#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */ 395#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max num of sects on one chip */ 396 397#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (in ms) */ 398#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ 399 400#define CONFIG_ENV_IS_IN_FLASH 1 401#define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ 402#define CONFIG_ENV_SECT_SIZE 0x40000 /* see README - env sect real size */ 403#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE) 404#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ 405 406/*----------------------------------------------------------------------- 407 * Cache Configuration 408 */ 409#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ 410#if defined(CONFIG_CMD_KGDB) 411#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value*/ 412#endif 413 414/*----------------------------------------------------------------------- 415 * HIDx - Hardware Implementation-dependent Registers 2-11 416 *----------------------------------------------------------------------- 417 * HID0 also contains cache control - initially enable both caches and 418 * invalidate contents, then the final state leaves only the instruction 419 * cache enabled. Note that Power-On and Hard reset invalidate the caches, 420 * but Soft reset does not. 421 * 422 * HID1 has only read-only information - nothing to set. 423 */ 424#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ 425 HID0_IFEM|HID0_ABE) 426#ifdef DEBUG 427#define CONFIG_SYS_HID0_FINAL 0 428#else 429#define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE) 430#endif 431#define CONFIG_SYS_HID2 0 432 433/*----------------------------------------------------------------------- 434 * RMR - Reset Mode Register 5-5 435 *----------------------------------------------------------------------- 436 * turn on Checkstop Reset Enable 437 */ 438#ifdef DEBUG 439#define CONFIG_SYS_RMR 0 440#else 441#define CONFIG_SYS_RMR RMR_CSRE 442#endif 443 444/*----------------------------------------------------------------------- 445 * BCR - Bus Configuration 4-25 446 *----------------------------------------------------------------------- 447 */ 448#define CONFIG_SYS_BCR (BCR_ETM) 449 450/*----------------------------------------------------------------------- 451 * SIUMCR - SIU Module Configuration 4-31 452 *----------------------------------------------------------------------- 453 */ 454#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC10|SIUMCR_L2CPC01|\ 455 SIUMCR_APPC10|SIUMCR_MMR11) 456 457/*----------------------------------------------------------------------- 458 * SYPCR - System Protection Control 4-35 459 * SYPCR can only be written once after reset! 460 *----------------------------------------------------------------------- 461 * Watchdog & Bus Monitor Timer max, 60x & Local Bus Monitor enable 462 */ 463#if defined(CONFIG_WATCHDOG) 464#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ 465 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) 466#else 467#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ 468 SYPCR_SWRI|SYPCR_SWP) 469#endif /* CONFIG_WATCHDOG */ 470 471/*----------------------------------------------------------------------- 472 * TMCNTSC - Time Counter Status and Control 4-40 473 *----------------------------------------------------------------------- 474 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, 475 * and enable Time Counter 476 */ 477#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) 478 479/*----------------------------------------------------------------------- 480 * PISCR - Periodic Interrupt Status and Control 4-42 481 *----------------------------------------------------------------------- 482 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable 483 * Periodic timer 484 */ 485#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) 486 487/*----------------------------------------------------------------------- 488 * SCCR - System Clock Control 9-8 489 *----------------------------------------------------------------------- 490 * Ensure DFBRG is Divide by 16 491 */ 492#define CONFIG_SYS_SCCR (SCCR_DFBRG01) 493 494/*----------------------------------------------------------------------- 495 * RCCR - RISC Controller Configuration 13-7 496 *----------------------------------------------------------------------- 497 */ 498#define CONFIG_SYS_RCCR 0 499 500/* 501 * Init Memory Controller: 502 * 503 * Bank Bus Machine PortSz Device 504 * ---- --- ------- ------ ------ 505 * 0 60x GPCM 32 bit FLASH 506 * 1 60x GPCM 32 bit FLASH (same as 0 - unused for now) 507 * 2 60x SDRAM 64 bit SDRAM 508 * 3 Local UPMC 8 bit Main Xilinx configuration 509 * 4 Local GPCM 32 bit Main Xilinx register mode 510 * 5 Local UPMB 32 bit Main Xilinx port mode 511 * 6 Local UPMC 8 bit Mezz Xilinx configuration 512 */ 513 514/* 515 * Bank 0 - FLASH 516 * 517 * Quotes from the HYMOD IO Board Reference manual: 518 * 519 * "The flash memory is two Intel StrataFlash chips, each configured for 520 * 16 bit operation and connected to give a 32 bit wide port." 521 * 522 * "The chip select logic is configured to respond to both *CS0 and *CS1. 523 * Therefore the FLASH memory will be mapped to both bank 0 and bank 1. 524 * It is suggested that bank 0 be read-only and bank 1 be read/write. The 525 * FLASH will then appear as ROM during boot." 526 * 527 * Initially, we are only going to use bank 0 in read/write mode. 528 */ 529 530/* 32 bit, read-write, GPCM on 60x bus */ 531#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE&BRx_BA_MSK)|\ 532 BRx_PS_32|BRx_MS_GPCM_P|BRx_V) 533/* up to 32 Mb */ 534#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(32)|ORxG_CSNT|ORxG_ACS_DIV2|ORxG_SCY_10_CLK) 535 536/* 537 * Bank 2 - SDRAM 538 * 539 * Quotes from the HYMOD IO Board Reference manual: 540 * 541 * "The main memory is implemented using TC59SM716FTL-10 SDRAM and has a 542 * fixed size of 64 Mbytes. The Toshiba TC59SM716FTL-10 is a CMOS synchronous 543 * dynamic random access memory organised as 4 banks by 4096 rows by 512 544 * columns by 16 bits. Four chips provide a 64-bit port on the 60x bus." 545 * 546 * "The locations in SDRAM are accessed using multiplexed address pins to 547 * specify row and column. The pins also act to specify commands. The state 548 * of the inputs *RAS, *CAS and *WE defines the required action. The a10/AP 549 * pin may function as a row address or as the AUTO PRECHARGE control line, 550 * depending on the cycle type. The 60x bus SDRAM machine allows the MPC8260 551 * address lines to be configured to the required multiplexing scheme." 552 */ 553 554#define CONFIG_SYS_SDRAM_SIZE 64 555 556/* 64 bit, read-write, SDRAM on 60x bus */ 557#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE&BRx_BA_MSK)|\ 558 BRx_PS_64|BRx_MS_SDRAM_P|BRx_V) 559/* 64 Mb, 4 int banks per dev, row start addr bit = A6, 12 row addr lines */ 560#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM_SIZE)|\ 561 ORxS_BPD_4|ORxS_ROWST_PBI1_A6|ORxS_NUMR_12) 562 563/* 564 * The 60x Bus SDRAM Mode Register (PDSMR) is set as follows: 565 * 566 * Page Based Interleaving, Refresh Enable, Address Multiplexing where A5 567 * is output on A16 pin (A6 on A17, and so on), use address pins A14-A16 568 * as bank select, A7 is output on SDA10 during an ACTIVATE command, 569 * earliest timing for ACTIVATE command after REFRESH command is 6 clocks, 570 * earliest timing for ACTIVATE or REFRESH command after PRECHARGE command 571 * is 2 clocks, earliest timing for READ/WRITE command after ACTIVATE 572 * command is 2 clocks, earliest timing for PRECHARGE after last data 573 * was read is 1 clock, earliest timing for PRECHARGE after last data 574 * was written is 1 clock, CAS Latency is 2. 575 */ 576 577#define CONFIG_SYS_PSDMR (PSDMR_PBI|PSDMR_SDAM_A16_IS_A5|\ 578 PSDMR_BSMA_A14_A16|PSDMR_SDA10_PBI1_A7|\ 579 PSDMR_RFRC_6_CLK|PSDMR_PRETOACT_2W|\ 580 PSDMR_ACTTORW_2W|PSDMR_LDOTOPRE_1C|\ 581 PSDMR_WRC_1C|PSDMR_CL_2) 582 583/* 584 * The 60x bus-assigned SDRAM Refresh Timer (PSRT) (10-31) and the Refresh 585 * Timers Prescale (PTP) value in the Memory Refresh Timer Prescaler Register 586 * (MPTPR) (10-32) must also be set up (it used to be called the Periodic Timer 587 * Prescaler, hence the P instead of the R). The refresh timer period is given 588 * by (note that there was a change in the 8260 UM Errata): 589 * 590 * TimerPeriod = (PSRT + 1) / Fmptc 591 * 592 * where Fmptc is the BusClock divided by PTP. i.e. 593 * 594 * TimerPeriod = (PSRT + 1) / (BusClock / PTP) 595 * 596 * or 597 * 598 * TImerPeriod = (PTP * (PSRT + 1)) / BusClock 599 * 600 * The requirement for the Toshiba TC59SM716FTL-10 is that there must be 601 * 4K refresh cycles every 64 ms. i.e. one refresh cycle every 64000/4096 602 * = 15.625 usecs. 603 * 604 * So PTP * (PSRT + 1) <= 15.625 * BusClock. At 66.666MHz, PSRT=31 and PTP=32 605 * appear to be reasonable. 606 */ 607 608#ifdef DEBUG 609#define CONFIG_SYS_PSRT 39 610#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV8 611#else 612#define CONFIG_SYS_PSRT 31 613#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32 614#endif 615 616/* 617 * Banks 3,4,5 and 6 - FPGA access 618 * 619 * Quotes from the HYMOD IO Board Reference manual: 620 * 621 * "The IO Board is fitted with a Xilinx XCV300E main FPGA. Provision is made 622 * for configuring an optional FPGA on the mezzanine interface. 623 * 624 * Access to the FPGAs may be divided into several catagories: 625 * 626 * 1. Configuration 627 * 2. Register mode access 628 * 3. Port mode access 629 * 630 * The main FPGA is supported for modes 1, 2 and 3. The mezzanine FPGA can be 631 * configured only (mode 1). Consequently there are four access types. 632 * 633 * To improve interface performance and simplify software design, the four 634 * possible access types are separately mapped to different memory banks. 635 * 636 * All are accessed using the local bus." 637 * 638 * Device Mode Memory Bank Machine Port Size Access 639 * 640 * Main Configuration 3 UPMC 8bit R/W 641 * Main Register 4 GPCM 32bit R/W 642 * Main Port 5 UPMB 32bit R/W 643 * Mezzanine Configuration 6 UPMC 8bit W/O 644 * 645 * "Note that mezzanine mode 1 access is write-only." 646 */ 647 648/* all the bank sizes must be a power of two, greater or equal to 32768 */ 649#define FPGA_MAIN_CFG_BASE (CONFIG_SYS_FPGA_BASE) 650#define FPGA_MAIN_CFG_SIZE 32768 651#define FPGA_MAIN_REG_BASE (FPGA_MAIN_CFG_BASE + FPGA_MAIN_CFG_SIZE) 652#define FPGA_MAIN_REG_SIZE 32768 653#define FPGA_MAIN_PORT_BASE (FPGA_MAIN_REG_BASE + FPGA_MAIN_REG_SIZE) 654#define FPGA_MAIN_PORT_SIZE 32768 655#define FPGA_MEZZ_CFG_BASE (FPGA_MAIN_PORT_BASE + FPGA_MAIN_PORT_SIZE) 656#define FPGA_MEZZ_CFG_SIZE 32768 657 658/* 8 bit, read-write, UPMC */ 659#define CONFIG_SYS_BR3_PRELIM (FPGA_MAIN_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V) 660/* up to 32Kbyte, burst inhibit */ 661#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(FPGA_MAIN_CFG_SIZE)|ORxU_BI) 662 663/* 32 bit, read-write, GPCM */ 664#define CONFIG_SYS_BR4_PRELIM (FPGA_MAIN_REG_BASE|BRx_PS_32|BRx_MS_GPCM_L|BRx_V) 665/* up to 32Kbyte */ 666#define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(FPGA_MAIN_REG_SIZE)) 667 668/* 32 bit, read-write, UPMB */ 669#define CONFIG_SYS_BR5_PRELIM (FPGA_MAIN_PORT_BASE|BRx_PS_32|BRx_MS_UPMB|BRx_V) 670/* up to 32Kbyte */ 671#define CONFIG_SYS_OR5_PRELIM (P2SZ_TO_AM(FPGA_MAIN_PORT_SIZE)|ORxU_BI) 672 673/* 8 bit, write-only, UPMC */ 674#define CONFIG_SYS_BR6_PRELIM (FPGA_MEZZ_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V) 675/* up to 32Kbyte, burst inhibit */ 676#define CONFIG_SYS_OR6_PRELIM (P2SZ_TO_AM(FPGA_MEZZ_CFG_SIZE)|ORxU_BI) 677 678/*----------------------------------------------------------------------- 679 * MBMR - Machine B Mode 10-27 680 *----------------------------------------------------------------------- 681 */ 682#define CONFIG_SYS_MBMR (MxMR_BSEL|MxMR_OP_NORM) /* XXX - needs more */ 683 684/*----------------------------------------------------------------------- 685 * MCMR - Machine C Mode 10-27 686 *----------------------------------------------------------------------- 687 */ 688#define CONFIG_SYS_MCMR (MxMR_BSEL|MxMR_DSx_2_CYCL) /* XXX - needs more */ 689 690/* 691 * FPGA I/O Port/Bit information 692 */ 693 694#define FPGA_MAIN_PROG_PORT IOPIN_PORTA 695#define FPGA_MAIN_PROG_PIN 4 /* PA4 */ 696#define FPGA_MAIN_INIT_PORT IOPIN_PORTA 697#define FPGA_MAIN_INIT_PIN 5 /* PA5 */ 698#define FPGA_MAIN_DONE_PORT IOPIN_PORTA 699#define FPGA_MAIN_DONE_PIN 6 /* PA6 */ 700 701#define FPGA_MEZZ_PROG_PORT IOPIN_PORTA 702#define FPGA_MEZZ_PROG_PIN 0 /* PA0 */ 703#define FPGA_MEZZ_INIT_PORT IOPIN_PORTA 704#define FPGA_MEZZ_INIT_PIN 1 /* PA1 */ 705#define FPGA_MEZZ_DONE_PORT IOPIN_PORTA 706#define FPGA_MEZZ_DONE_PIN 2 /* PA2 */ 707#define FPGA_MEZZ_ENABLE_PORT IOPIN_PORTA 708#define FPGA_MEZZ_ENABLE_PIN 3 /* PA3 */ 709 710/* 711 * FPGA Interrupt configuration 712 */ 713#define FPGA_MAIN_IRQ SIU_INT_IRQ2 714 715/* 716 * JFFS2 partitions 717 * 718 */ 719/* No command line, one static partition, whole device */ 720#undef CONFIG_CMD_MTDPARTS 721#define CONFIG_JFFS2_DEV "nor0" 722#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF 723#define CONFIG_JFFS2_PART_OFFSET 0x00000000 724 725/* mtdparts command line support */ 726/* 727#define CONFIG_CMD_MTDPARTS 728#define MTDIDS_DEFAULT "" 729#define MTDPARTS_DEFAULT "" 730*/ 731 732#endif /* __CONFIG_H */ 733