1/* 2 * (C) Copyright 2008 3 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8#ifndef __CONFIG_H 9#define __CONFIG_H 10 11/* 12 * High Level Configuration Options 13 * (easy to change) 14 */ 15 16#define CONFIG_8260 1 17#define CONFIG_MPC8260 1 18#define CONFIG_MUAS3001 1 19 20#define CONFIG_SYS_TEXT_BASE 0xFF000000 21 22#define CONFIG_CPM2 1 /* Has a CPM2 */ 23 24/* Do boardspecific init */ 25#define CONFIG_BOARD_EARLY_INIT_R 1 26 27/* enable Watchdog */ 28#define CONFIG_WATCHDOG 1 29 30/* 31 * Select serial console configuration 32 * 33 * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then 34 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 35 * for SCC). 36 */ 37#define CONFIG_CONS_ON_SMC /* Console is on SMC */ 38#undef CONFIG_CONS_ON_SCC /* It's not on SCC */ 39#undef CONFIG_CONS_NONE /* It's not on external UART */ 40#if defined(CONFIG_MUAS_DEV_BOARD) 41#define CONFIG_CONS_INDEX 2 /* SMC2 is used for console */ 42#else 43#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */ 44#endif 45 46/* 47 * Select ethernet configuration 48 * 49 * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, 50 * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for 51 * SCC, 1-3 for FCC) 52 * 53 * If CONFIG_ETHER_NONE is defined, then either the ethernet routines 54 * must be defined elsewhere (as for the console), or CONFIG_CMD_NET 55 * must be unset. 56 */ 57#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */ 58#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */ 59#undef CONFIG_ETHER_NONE /* No external Ethernet */ 60 61#define CONFIG_ETHER_INDEX 1 62#define CONFIG_ETHER_ON_FCC1 63#define CONFIG_HAS_ETH0 64#define FCC_ENET 65 66/* 67 * - Rx-CLK is CLK11 68 * - Tx-CLK is CLK12 69 */ 70# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12) 71# define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK) 72/* 73 * - RAM for BD/Buffers is on the 60x Bus (see 28-13) 74 */ 75# define CONFIG_SYS_CPMFCR_RAMTYPE (0) 76/* know on local Bus */ 77/* define CONFIG_SYS_CPMFCR_RAMTYPE (CPMFCR_DTB | CPMFCR_BDB) */ 78/* 79 * - Enable Full Duplex in FSMR 80 */ 81# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) 82 83#define CONFIG_MII /* MII PHY management */ 84#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ 85# define CONFIG_SYS_PHY_ADDR 1 86/* 87 * GPIO pins used for bit-banged MII communications 88 */ 89#define MDIO_PORT 0 /* Port A */ 90#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ 91 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) 92#define MDC_DECLARE MDIO_DECLARE 93 94 95#define CONFIG_SYS_MDIO_PIN 0x00200000 /* PA10 */ 96#define CONFIG_SYS_MDC_PIN 0x00400000 /* PA9 */ 97 98#define MDIO_ACTIVE (iop->pdir |= CONFIG_SYS_MDIO_PIN) 99#define MDIO_TRISTATE (iop->pdir &= ~CONFIG_SYS_MDIO_PIN) 100#define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0) 101 102#define MDIO(bit) if(bit) iop->pdat |= CONFIG_SYS_MDIO_PIN; \ 103 else iop->pdat &= ~CONFIG_SYS_MDIO_PIN 104 105#define MDC(bit) if(bit) iop->pdat |= CONFIG_SYS_MDC_PIN; \ 106 else iop->pdat &= ~CONFIG_SYS_MDC_PIN 107 108#define MIIDELAY udelay(1) 109 110#ifndef CONFIG_8260_CLKIN 111#define CONFIG_8260_CLKIN 66000000 /* in Hz */ 112#endif 113 114#define CONFIG_BAUDRATE 115200 115 116/* 117 * Command line configuration. 118 */ 119#include <config_cmd_default.h> 120 121#define CONFIG_CMD_DTT 122#define CONFIG_CMD_ECHO 123#define CONFIG_CMD_IMMAP 124#define CONFIG_CMD_MII 125#define CONFIG_CMD_PING 126#define CONFIG_CMD_I2C 127 128/* 129 * Default environment settings 130 */ 131#define CONFIG_EXTRA_ENV_SETTINGS \ 132 "netdev=eth0\0" \ 133 "u-boot_addr_r=100000\0" \ 134 "kernel_addr_r=200000\0" \ 135 "fdt_addr_r=400000\0" \ 136 "rootpath=/opt/eldk/ppc_6xx\0" \ 137 "u-boot=muas3001/u-boot.bin\0" \ 138 "bootfile=muas3001/uImage\0" \ 139 "fdt_file=muas3001/muas3001.dtb\0" \ 140 "ramdisk_file=uRamdisk\0" \ 141 "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ 142 "update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; " \ 143 "cp.b ${u-boot_addr_r} ff000000 ${filesize};" \ 144 "prot on ff000000 ff03ffff\0" \ 145 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 146 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 147 "nfsroot=${serverip}:${rootpath}\0" \ 148 "addcons=setenv bootargs ${bootargs} console=ttyCPM0,${baudrate}\0" \ 149 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 150 "addip=setenv bootargs ${bootargs} " \ 151 "ip=${ipaddr}:${serverip}:${gatewayip}:" \ 152 "${netmask}:${hostname}:${netdev}:off panic=1\0" \ 153 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ 154 "tftp ${fdt_addr_r} ${fdt_file}; run nfsargs addip addcons;" \ 155 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ 156 "net_self=tftp ${kernel_addr_r} ${bootfile}; " \ 157 "tftp ${fdt_addr_r} ${fdt_file}; " \ 158 "tftp ${ramdisk_addr} ${ramdisk_file}; " \ 159 "run ramargs addip; " \ 160 "bootm ${kernel_addr_r} ${ramdisk_addr} ${fdt_addr_r}\0" \ 161 "ramdisk_addr=ff210000\0" \ 162 "kernel_addr=ff050000\0" \ 163 "fdt_addr=ff200000\0" \ 164 "flash_self=run ramargs addip addcons;bootm ${kernel_addr}" \ 165 " ${ramdisk_addr} ${fdt_addr}\0" \ 166 "updateramdisk=era ${ramdisk_addr} +1f0000;tftpb ${kernel_addr_r}" \ 167 " ${ramdisk_file};" \ 168 "cp.b ${kernel_addr_r} ${ramdisk_addr} ${filesize}\0" \ 169 "updatekernel=era ${kernel_addr} +1b0000;tftpb ${kernel_addr_r}" \ 170 " ${bootfile};" \ 171 "cp.b ${kernel_addr_r} ${kernel_addr} ${filesize}\0" \ 172 "updatefdt=era ${fdt_addr} +10000;tftpb ${fdt_addr_r} ${fdt_file};" \ 173 "cp.b ${fdt_addr_r} ${fdt_addr} ${filesize}\0" \ 174 "" 175 176#define CONFIG_BOOTCOMMAND "run net_nfs" 177#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 178 179/* 180 * Miscellaneous configurable options 181 */ 182#define CONFIG_SYS_HUSH_PARSER 183#define CONFIG_SYS_LONGHELP /* undef to save memory */ 184#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 185#if defined(CONFIG_CMD_KGDB) 186#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 187#else 188#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 189#endif 190#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 191#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 192#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 193 194#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ 195#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ 196 197#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 198 199#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 200 201#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } 202 203#define CONFIG_SYS_SDRAM_BASE 0x00000000 204#define CONFIG_SYS_FLASH_BASE 0xFF000000 205#define CONFIG_SYS_FLASH_SIZE 32 206#define CONFIG_SYS_FLASH_CFI 207#define CONFIG_FLASH_CFI_DRIVER 208#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ 209#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ 210 211#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 212 213#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 214#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 215#define CONFIG_SYS_RAMBOOT 216#endif 217 218#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256KB for Monitor */ 219 220#define CONFIG_ENV_IS_IN_FLASH 221 222#ifdef CONFIG_ENV_IS_IN_FLASH 223#define CONFIG_ENV_SECT_SIZE 0x10000 224#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 225#endif /* CONFIG_ENV_IS_IN_FLASH */ 226 227/* 228 * I2C Bus 229 */ 230#define CONFIG_HARD_I2C 1 /* To enable I2C support */ 231#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ 232#define CONFIG_SYS_I2C_SLAVE 0x7F 233 234#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 235/* I2C SYSMON (LM75, AD7414 is almost compatible) */ 236#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ 237#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ 238#define CONFIG_SYS_DTT_MAX_TEMP 70 239#define CONFIG_SYS_DTT_LOW_TEMP -30 240#define CONFIG_SYS_DTT_HYSTERESIS 3 241 242#define CONFIG_SYS_IMMR 0xF0000000 243#define CONFIG_SYS_DEFAULT_IMMR 0x0F010000 244 245#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 246#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */ 247#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 248#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 249 250/* Hard reset configuration word */ 251#define CONFIG_SYS_HRCW_MASTER 0x0E028200 /* BPS=11 CIP=1 ISB=010 BMS=1 */ 252 253/* No slaves */ 254#define CONFIG_SYS_HRCW_SLAVE1 0 255#define CONFIG_SYS_HRCW_SLAVE2 0 256#define CONFIG_SYS_HRCW_SLAVE3 0 257#define CONFIG_SYS_HRCW_SLAVE4 0 258#define CONFIG_SYS_HRCW_SLAVE5 0 259#define CONFIG_SYS_HRCW_SLAVE6 0 260#define CONFIG_SYS_HRCW_SLAVE7 0 261 262#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */ 263#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 264 265#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */ 266#if defined(CONFIG_CMD_KGDB) 267# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 268#endif 269 270#define CONFIG_SYS_HID0_INIT 0 271#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE) 272 273#define CONFIG_SYS_HID2 0 274 275#define CONFIG_SYS_SIUMCR 0x00200000 276#define CONFIG_SYS_BCR 0x004c0000 277#define CONFIG_SYS_SCCR 0x0 278 279/*----------------------------------------------------------------------- 280 * SYPCR - System Protection Control 4-35 281 * SYPCR can only be written once after reset! 282 *----------------------------------------------------------------------- 283 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable 284 */ 285#if defined(CONFIG_WATCHDOG) 286#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ 287 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) 288#else 289#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ 290 SYPCR_SWRI|SYPCR_SWP) 291#endif /* CONFIG_WATCHDOG */ 292 293/*----------------------------------------------------------------------- 294 * RMR - Reset Mode Register 5-5 295 *----------------------------------------------------------------------- 296 * turn on Checkstop Reset Enable 297 */ 298#define CONFIG_SYS_RMR 0 299 300/*----------------------------------------------------------------------- 301 * TMCNTSC - Time Counter Status and Control 4-40 302 *----------------------------------------------------------------------- 303 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, 304 * and enable Time Counter 305 */ 306#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) 307 308/*----------------------------------------------------------------------- 309 * PISCR - Periodic Interrupt Status and Control 4-42 310 *----------------------------------------------------------------------- 311 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable 312 * Periodic timer 313 */ 314#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) 315 316/*----------------------------------------------------------------------- 317 * RCCR - RISC Controller Configuration 13-7 318 *----------------------------------------------------------------------- 319 */ 320#define CONFIG_SYS_RCCR 0 321 322/* 323 * Init Memory Controller: 324 * 325 * Bank Bus Machine PortSz Device 326 * ---- --- ------- ------ ------ 327 * 0 60x GPCM 32 bit FLASH 328 * 1 60x SDRAM 64 bit SDRAM 329 * 4 60x GPCM 16 bit I/O Ctrl 330 * 331 */ 332/* Bank 0 - FLASH 333 */ 334#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ 335 BRx_PS_32 |\ 336 BRx_MS_GPCM_P |\ 337 BRx_V) 338 339#define CONFIG_SYS_OR0_PRELIM (0xff000020) 340 341/* Bank 1 - 60x bus SDRAM 342 */ 343#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (256 << 20) /* less than 256 MB */ 344 345#define CONFIG_SYS_MPTPR 0x2800 346 347/*----------------------------------------------------------------------------- 348 * Address for Mode Register Set (MRS) command 349 *----------------------------------------------------------------------------- 350 */ 351#define CONFIG_SYS_MRS_OFFS 0x00000110 352#define CONFIG_SYS_PSRT 0x13 353 354#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ 355 BRx_PS_64 |\ 356 BRx_MS_SDRAM_P |\ 357 BRx_V) 358 359#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1_LITTLE 360 361/* SDRAM initialization values 362*/ 363#define CONFIG_SYS_OR1_LITTLE ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ 364 ORxS_BPD_4 |\ 365 ORxS_ROWST_PBI1_A7 |\ 366 ORxS_NUMR_12) 367 368#define CONFIG_SYS_PSDMR_LITTLE 0x004b36a3 369 370#define CONFIG_SYS_OR1_BIG ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ 371 ORxS_BPD_4 |\ 372 ORxS_ROWST_PBI1_A4 |\ 373 ORxS_NUMR_12) 374 375#define CONFIG_SYS_PSDMR_BIG 0x014f36a3 376 377/* IO on CS4 initialization values 378*/ 379#define CONFIG_SYS_IO_BASE 0xc0000000 380#define CONFIG_SYS_IO_SIZE 1 381 382#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_IO_BASE & BRx_BA_MSK) |\ 383 BRx_PS_16 | BRx_MS_GPCM_L | BRx_V) 384 385#define CONFIG_SYS_OR4_PRELIM (0xfff80020) 386 387#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */ 388 389/* pass open firmware flat tree */ 390#define CONFIG_OF_LIBFDT 1 391#define CONFIG_OF_BOARD_SETUP 1 392 393#define OF_TBCLK (bd->bi_busfreq / 4) 394#if defined(CONFIG_MUAS_DEV_BOARD) 395#define OF_STDOUT_PATH "/soc/cpm/serial@11a90" 396#else 397#define OF_STDOUT_PATH "/soc/cpm/serial@11a80" 398#endif 399 400#endif /* __CONFIG_H */ 401