1/* 2 * (C) Copyright 2003-2010 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8/* 9 * board/config.h - configuration options, board specific 10 * changes for 16M board 11 */ 12 13#ifndef __CONFIG_H 14#define __CONFIG_H 15 16/* 17 * High Level Configuration Options 18 * (easy to change) 19 */ 20 21#undef CONFIG_MPC860 22#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ 23#define CONFIG_RPXLITE 1 /* QUANTUM is the RPXlite clone */ 24#define CONFIG_RMU 1 /* The QUNATUM is based on our RMU */ 25 26#define CONFIG_SYS_TEXT_BASE 0xfff00000 27 28#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 29#undef CONFIG_8xx_CONS_SMC2 30#undef CONFIG_8xx_CONS_NONE 31#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */ 32#if 0 33#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ 34#else 35#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 36#endif 37 38/* default developmenmt environment */ 39 40#define CONFIG_ETHADDR 00:0B:17:00:00:00 41 42#define CONFIG_IPADDR 10.10.69.10 43#define CONFIG_SERVERIP 10.10.69.49 44#define CONFIG_NETMASK 255.255.255.0 45#define CONFIG_HOSTNAME QUANTUM 46#define CONFIG_ROOTPATH "/opt/eldk/pcc_8xx" 47 48#define CONFIG_BOOTARGS "root=/dev/ram rw" 49 50#define CONFIG_BOOTCOMMAND "bootm ff000000" 51 52#define CONFIG_EXTRA_ENV_SETTINGS \ 53 "serial#=12345\0" \ 54 "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \ 55 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 56 "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" 57 58/* 59 * Select the more full-featured memory test (Barr embedded systems) 60 */ 61#define CONFIG_SYS_ALT_MEMTEST 62 63#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 64#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 65 66 67/* M48T02 Paralled access timekeeper with same interface as the M48T35A*/ 68#define CONFIG_RTC_M48T35A 1 69 70#if 0 71#define CONFIG_WATCHDOG 1 /* watchdog enabled */ 72#else 73#undef CONFIG_WATCHDOG 74#endif 75 76/* NVRAM and RTC */ 77#define CONFIG_SYS_NVRAM_BASE_ADDR 0xFA000000 78#define CONFIG_SYS_NVRAM_SIZE 2048 79 80 81/* 82 * Command line configuration. 83 */ 84#include <config_cmd_default.h> 85 86#define CONFIG_CMD_DATE 87#define CONFIG_CMD_DHCP 88#define CONFIG_CMD_NFS 89#define CONFIG_CMD_PING 90#define CONFIG_CMD_REGINFO 91#define CONFIG_CMD_SNTP 92 93 94/* 95 * BOOTP options 96 */ 97#define CONFIG_BOOTP_SUBNETMASK 98#define CONFIG_BOOTP_GATEWAY 99#define CONFIG_BOOTP_HOSTNAME 100#define CONFIG_BOOTP_BOOTPATH 101#define CONFIG_BOOTP_BOOTFILESIZE 102 103 104#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */ 105#define CONFIG_AUTOBOOT_PROMPT \ 106 "\nEnter password - autoboot in %d sec...\n", bootdelay 107#define CONFIG_AUTOBOOT_DELAY_STR "system" 108/* 109 * Miscellaneous configurable options 110 */ 111#define CONFIG_SYS_LONGHELP /* undef to save memory */ 112#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 113#if defined(CONFIG_CMD_KGDB) 114#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 115#else 116#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 117#endif 118#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 119#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 120#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 121 122#define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest works on */ 123#define CONFIG_SYS_MEMTEST_END 0x01f00000 /* 256K ... 15 MB in DRAM */ 124 125#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 126 127#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 128 129/* 130 * Low Level Configuration Settings 131 * (address mappings, register initial values, etc.) 132 * You should know what you are doing if you make changes here. 133 */ 134/*----------------------------------------------------------------------- 135 * Internal Memory Mapped Register 136 */ 137#define CONFIG_SYS_IMMR 0xFA200000 138 139/*----------------------------------------------------------------------- 140 * Definitions for initial stack pointer and data area (in DPRAM) 141 */ 142#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 143#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ 144#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 145#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 146 147/*----------------------------------------------------------------------- 148 * Start addresses for the final memory configuration 149 * (Set up by the startup code) 150 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 151 */ 152#define CONFIG_SYS_SDRAM_BASE 0x00000000 153#define CONFIG_SYS_FLASH_BASE 0xFF000000 154 155#if 1 156 #define CONFIG_FLASH_CFI_DRIVER 157#else 158 #undef CONFIG_FLASH_CFI_DRIVER 159#endif 160 161 162#ifdef CONFIG_FLASH_CFI_DRIVER 163 #define CONFIG_SYS_FLASH_CFI 1 164 #undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE 165 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} 166#endif 167 168/*%%% #define CONFIG_SYS_FLASH_BASE 0xFFF00000 */ 169#if defined(DEBUG) || defined(CONFIG_CMD_IDE) 170#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 171#else 172#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ 173#endif 174#define CONFIG_SYS_MONITOR_BASE 0xFFF00000 175/*%%% #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE */ 176#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 177 178/* 179 * For booting Linux, the board info and command line data 180 * have to be in the first 8 MB of memory, since this is 181 * the maximum mapped by the Linux kernel during initialization. 182 */ 183#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 184 185/*----------------------------------------------------------------------- 186 * FLASH organization 187 */ 188#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 189#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ 190 191#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 192#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 193 194#define CONFIG_ENV_IS_IN_FLASH 1 195#define CONFIG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector absolute address 0xfff40000*/ 196#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ 197#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 198#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) 199 200/* Address and size of Redundant Environment Sector */ 201#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) 202#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 203 204/* FPGA */ 205#define CONFIG_MISC_INIT_R 206#define CONFIG_SYS_FPGA_SPARTAN2 207#define CONFIG_SYS_FPGA_PROG_FEEDBACK 208 209 210/*----------------------------------------------------------------------- 211 * Reset address 212 */ 213#define CONFIG_SYS_RESET_ADDRESS ((ulong)((((immap_t *)CONFIG_SYS_IMMR)->im_clkrst.res))) 214 215/*----------------------------------------------------------------------- 216 * Cache Configuration 217 */ 218#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 219#if defined(CONFIG_CMD_KGDB) 220#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 221#endif 222 223/*----------------------------------------------------------------------- 224 * SYPCR - System Protection Control 11-9 225 * SYPCR can only be written once after reset! 226 *----------------------------------------------------------------------- 227 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 228 */ 229#if defined(CONFIG_WATCHDOG) 230#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 231 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 232#else 233#define CONFIG_SYS_SYPCR (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 234#endif 235 236/*----------------------------------------------------------------------- 237 * SIUMCR - SIU Module Configuration 11-6 238 *----------------------------------------------------------------------- 239 * PCMCIA config., multi-function pin tri-state 240 */ 241#define CONFIG_SYS_SIUMCR (SIUMCR_MLRC10) 242 243/*----------------------------------------------------------------------- 244 * TBSCR - Time Base Status and Control 11-26 245 *----------------------------------------------------------------------- 246 * Clear Reference Interrupt Status, Timebase freezing enabled 247 */ 248#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE) 249 250/*----------------------------------------------------------------------- 251 * RTCSC - Real-Time Clock Status and Control Register 11-27 252 *----------------------------------------------------------------------- 253 */ 254/*%%%#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */ 255#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_RTE) 256 257/*----------------------------------------------------------------------- 258 * PISCR - Periodic Interrupt Status and Control 11-31 259 *----------------------------------------------------------------------- 260 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 261 */ 262#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 263 264/*----------------------------------------------------------------------- 265 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 266 *----------------------------------------------------------------------- 267 * Reset PLL lock status sticky bit, timer expired status bit and timer 268 * interrupt status bit 269 * 270 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! 271 */ 272/* up to 50 MHz we use a 1:1 clock */ 273#define CONFIG_SYS_PLPRCR ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS ) 274 275/*----------------------------------------------------------------------- 276 * SCCR - System Clock and reset Control Register 15-27 277 *----------------------------------------------------------------------- 278 * Set clock output, timebase and RTC source and divider, 279 * power management and some other internal clocks 280 */ 281#define SCCR_MASK SCCR_EBDF00 282/* up to 50 MHz we use a 1:1 clock */ 283#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_TBS) 284 285/*----------------------------------------------------------------------- 286 * PCMCIA stuff 287 *----------------------------------------------------------------------- 288 * 289 */ 290#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 291#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 292#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 293#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 294#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 295#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 296#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 297#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 298 299/*----------------------------------------------------------------------- 300 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) 301 *----------------------------------------------------------------------- 302 */ 303 304#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ 305#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ 306 307#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 308#undef CONFIG_IDE_LED /* LED for ide not supported */ 309#undef CONFIG_IDE_RESET /* reset for ide not supported */ 310 311#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 312#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 313 314#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 315 316#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 317 318/* Offset for data I/O */ 319#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 320 321/* Offset for normal register accesses */ 322#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 323 324/* Offset for alternate registers */ 325#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 326 327/*----------------------------------------------------------------------- 328 * 329 *----------------------------------------------------------------------- 330 * 331 */ 332/*#define CONFIG_SYS_DER 0x2002000F*/ 333#define CONFIG_SYS_DER 0 334 335/* 336 * Init Memory Controller: 337 * 338 * BR0 and OR0 (FLASH) 339 */ 340 341#define FLASH_BASE_PRELIM 0xFE000000 /* FLASH base */ 342#define CONFIG_SYS_PRELIM_OR_AM 0xFE000000 /* OR addr mask */ 343 344/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */ 345#define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI) 346 347#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 348#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V) 349 350/* 351 * BR1 and OR1 (SDRAM) 352 * 353 */ 354#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */ 355#define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB */ 356 357/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 358#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000E00 359 360#define CONFIG_SYS_OR1_PRELIM (0xF0000000 | CONFIG_SYS_OR_TIMING_SDRAM ) /* map 256 MB */ 361#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 362 363/* RPXLITE mem setting */ 364#define CONFIG_SYS_BR3_PRELIM 0xFA400001 /* FPGA */ 365#define CONFIG_SYS_OR3_PRELIM 0xFFFF8910 366 367#define CONFIG_SYS_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */ 368#define CONFIG_SYS_OR4_PRELIM 0xFFFE0970 369 370/* 371 * Memory Periodic Timer Prescaler 372 */ 373 374/* periodic timer for refresh */ 375#define CONFIG_SYS_MAMR_PTA 20 376 377/* 378 * Refresh clock Prescalar 379 */ 380#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV2 381 382/* 383 * MAMR settings for SDRAM 384 */ 385 386/* 9 column SDRAM */ 387#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 388 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 389 MAMR_RLFA_16X | MAMR_WLFA_16X | MAMR_TLFA_16X) 390 391/* 392 * BCSRx 393 * 394 * Board Status and Control Registers 395 * 396 */ 397 398#define BCSR0 0xFA400000 399#define BCSR1 0xFA400001 400#define BCSR2 0xFA400002 401#define BCSR3 0xFA400003 402 403#define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */ 404#define BCSR0_ENNVRAM 0x02 /* CS4# Control */ 405#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */ 406#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */ 407#define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */ 408#define BCSR0_COLTEST 0x20 409#define BCSR0_ETHLPBK 0x40 410#define BCSR0_ETHEN 0x80 411 412#define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */ 413#define BCSR1_PCVCTL6 0x02 414#define BCSR1_PCVCTL5 0x04 415#define BCSR1_PCVCTL4 0x08 416#define BCSR1_IPB5SEL 0x10 417 418#define BCSR2_ENPA5HDR 0x08 /* USB Control */ 419#define BCSR2_ENUSBCLK 0x10 420#define BCSR2_USBPWREN 0x20 421#define BCSR2_USBSPD 0x40 422#define BCSR2_USBSUSP 0x80 423 424#define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */ 425#define BCSR3_BWNVR 0x02 /* NVRAM Battery */ 426#define BCSR3_RDY_BSY 0x04 /* Flash Operation */ 427#define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */ 428#define BCSR3_D27 0x10 /* Dip Switch settings */ 429#define BCSR3_D26 0x20 430#define BCSR3_D25 0x40 431#define BCSR3_D24 0x80 432 433#endif /* __CONFIG_H */ 434