1/* 2 * (C) Copyright 2000-2005 3 * Stefan Roese, DENX Software Engineering, sr@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8/* 9 * board/config.h - configuration options, board specific 10 */ 11 12#ifndef __CONFIG_H 13#define __CONFIG_H 14 15/* 16 * High Level Configuration Options 17 * (easy to change) 18 */ 19 20#define CONFIG_405GP 1 /* This is a PPC405 CPU */ 21#define CONFIG_4xx 1 /* ...member of PPC4xx family */ 22#define CONFIG_WALNUT 1 /* ...on a WALNUT board */ 23 /* ...or on a SYCAMORE board */ 24 25#define CONFIG_SYS_TEXT_BASE 0xFFFC0000 26 27/* 28 * Include common defines/options for all AMCC eval boards 29 */ 30#define CONFIG_HOSTNAME walnut 31#include "amcc-common.h" 32 33#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ 34 35#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ 36 37/* 38 * Default environment variables 39 */ 40#define CONFIG_EXTRA_ENV_SETTINGS \ 41 CONFIG_AMCC_DEF_ENV \ 42 CONFIG_AMCC_DEF_ENV_POWERPC \ 43 CONFIG_AMCC_DEF_ENV_PPC_OLD \ 44 CONFIG_AMCC_DEF_ENV_NOR_UPD \ 45 "kernel_addr=fff80000\0" \ 46 "ramdisk_addr=fff80000\0" \ 47 "" 48 49#define CONFIG_PHY_ADDR 1 /* PHY address */ 50#define CONFIG_HAS_ETH0 1 51 52#define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Walnut */ 53 54/* 55 * Commands additional to the ones defined in amcc-common.h 56 */ 57#define CONFIG_CMD_DATE 58#define CONFIG_CMD_PCI 59#define CONFIG_CMD_SDRAM 60#define CONFIG_CMD_SNTP 61 62#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */ 63 64/* 65 * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1. 66 * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31. 67 * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value. 68 * The Linux BASE_BAUD define should match this configuration. 69 * baseBaud = cpuClock/(uartDivisor*16) 70 * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock, 71 * set Linux BASE_BAUD to 403200. 72 */ 73#define CONFIG_CONS_INDEX 1 /* Use UART0 */ 74#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ 75#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ 76#define CONFIG_SYS_BASE_BAUD 691200 77 78/*----------------------------------------------------------------------- 79 * I2C stuff 80 *----------------------------------------------------------------------- 81 */ 82#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 83 84#define CONFIG_SYS_I2C_MULTI_EEPROMS 85#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1) 86#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 87#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 88#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 89 90/*----------------------------------------------------------------------- 91 * PCI stuff 92 *----------------------------------------------------------------------- 93 */ 94#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ 95#define PCI_HOST_FORCE 1 /* configure as pci host */ 96#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ 97 98#define CONFIG_PCI /* include pci support */ 99#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 100#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ 101#define CONFIG_PCI_PNP /* do pci plug-and-play */ 102 /* resource configuration */ 103#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 104 105#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ 106#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ 107#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ 108#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ 109#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ 110#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */ 111#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */ 112#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ 113 114/*----------------------------------------------------------------------- 115 * Start addresses for the final memory configuration 116 * (Set up by the startup code) 117 */ 118#define CONFIG_SYS_FLASH_BASE 0xFFF80000 119 120/* 121 * Define here the location of the environment variables (FLASH or NVRAM). 122 * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only 123 * supported for backward compatibility. 124 */ 125#if 1 126#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ 127#else 128#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ 129#endif 130 131/*----------------------------------------------------------------------- 132 * FLASH organization 133 */ 134#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */ 135#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ 136 137#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 138#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ 139 140#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 141#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 142 143#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ 144 145#define CONFIG_SYS_FLASH_ADDR0 0x5555 146#define CONFIG_SYS_FLASH_ADDR1 0x2aaa 147#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char 148 149#ifdef CONFIG_ENV_IS_IN_FLASH 150#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ 151#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) 152#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ 153 154/* Address and size of Redundant Environment Sector */ 155#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) 156#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 157#endif /* CONFIG_ENV_IS_IN_FLASH */ 158 159/*----------------------------------------------------------------------- 160 * NVRAM organization 161 */ 162#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */ 163#define CONFIG_SYS_NVRAM_SIZE 0x1ff8 /* NVRAM size */ 164 165#ifdef CONFIG_ENV_IS_IN_NVRAM 166#define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */ 167#define CONFIG_ENV_ADDR \ 168 (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */ 169#endif 170 171/*----------------------------------------------------------------------- 172 * External Bus Controller (EBC) Setup 173 */ 174 175/* Memory Bank 0 (Flash Bank 0) initialization */ 176#define CONFIG_SYS_EBC_PB0AP 0x9B015480 177#define CONFIG_SYS_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */ 178 179#define CONFIG_SYS_EBC_PB1AP 0x02815480 180#define CONFIG_SYS_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ 181 182#define CONFIG_SYS_EBC_PB2AP 0x04815A80 183#define CONFIG_SYS_EBC_PB2CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */ 184 185#define CONFIG_SYS_EBC_PB3AP 0x01815280 186#define CONFIG_SYS_EBC_PB3CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */ 187 188#define CONFIG_SYS_EBC_PB7AP 0x01815280 189#define CONFIG_SYS_EBC_PB7CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */ 190 191/*----------------------------------------------------------------------- 192 * External peripheral base address 193 *----------------------------------------------------------------------- 194 */ 195#define CONFIG_SYS_KEY_REG_BASE_ADDR 0xF0100000 196#define CONFIG_SYS_IR_REG_BASE_ADDR 0xF0200000 197#define CONFIG_SYS_FPGA_REG_BASE_ADDR 0xF0300000 198 199/*----------------------------------------------------------------------- 200 * Definitions for initial stack pointer and data area 201 */ 202#define CONFIG_SYS_INIT_DCACHE_CS 4 /* use cs # 4 for data cache memory */ 203 204#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* inside of SDRAM */ 205#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */ 206#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 207#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 208 209/*----------------------------------------------------------------------- 210 * Definitions for Serial Presence Detect EEPROM address 211 * (to get SDRAM settings) 212 */ 213#define SPD_EEPROM_ADDRESS 0x50 214 215#endif /* __CONFIG_H */ 216