1/* 2 * Copyright (C) 2009, DENX Software Engineering 3 * Author: John Rigby <jcrigby@gmail.com 4 * 5 * Based on arch-mx31/imx-regs.h 6 * Copyright (C) 2009 Ilya Yanok, 7 * Emcraft Systems <yanok@emcraft.com> 8 * and arch-mx27/imx-regs.h 9 * Copyright (C) 2007 Pengutronix, 10 * Sascha Hauer <s.hauer@pengutronix.de> 11 * Copyright (C) 2009 Ilya Yanok, 12 * Emcraft Systems <yanok@emcraft.com> 13 * 14 * SPDX-License-Identifier: GPL-2.0+ 15 */ 16 17#ifndef _IMX_REGS_H 18#define _IMX_REGS_H 19 20#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 21#include <asm/types.h> 22 23/* Clock Control Module (CCM) registers */ 24struct ccm_regs { 25 u32 mpctl; /* Core PLL Control */ 26 u32 upctl; /* USB PLL Control */ 27 u32 cctl; /* Clock Control */ 28 u32 cgr0; /* Clock Gating Control 0 */ 29 u32 cgr1; /* Clock Gating Control 1 */ 30 u32 cgr2; /* Clock Gating Control 2 */ 31 u32 pcdr[4]; /* PER Clock Dividers */ 32 u32 rcsr; /* CCM Status */ 33 u32 crdr; /* CCM Reset and Debug */ 34 u32 dcvr0; /* DPTC Comparator Value 0 */ 35 u32 dcvr1; /* DPTC Comparator Value 1 */ 36 u32 dcvr2; /* DPTC Comparator Value 2 */ 37 u32 dcvr3; /* DPTC Comparator Value 3 */ 38 u32 ltr0; /* Load Tracking 0 */ 39 u32 ltr1; /* Load Tracking 1 */ 40 u32 ltr2; /* Load Tracking 2 */ 41 u32 ltr3; /* Load Tracking 3 */ 42 u32 ltbr0; /* Load Tracking Buffer 0 */ 43 u32 ltbr1; /* Load Tracking Buffer 1 */ 44 u32 pcmr0; /* Power Management Control 0 */ 45 u32 pcmr1; /* Power Management Control 1 */ 46 u32 pcmr2; /* Power Management Control 2 */ 47 u32 mcr; /* Miscellaneous Control */ 48 u32 lpimr0; /* Low Power Interrupt Mask 0 */ 49 u32 lpimr1; /* Low Power Interrupt Mask 1 */ 50}; 51 52/* Enhanced SDRAM Controller (ESDRAMC) registers */ 53struct esdramc_regs { 54 u32 ctl0; /* control 0 */ 55 u32 cfg0; /* configuration 0 */ 56 u32 ctl1; /* control 1 */ 57 u32 cfg1; /* configuration 1 */ 58 u32 misc; /* miscellaneous */ 59 u32 pad[3]; 60 u32 cdly1; /* Delay Line 1 configuration debug */ 61 u32 cdly2; /* delay line 2 configuration debug */ 62 u32 cdly3; /* delay line 3 configuration debug */ 63 u32 cdly4; /* delay line 4 configuration debug */ 64 u32 cdly5; /* delay line 5 configuration debug */ 65 u32 cdlyl; /* delay line cycle length debug */ 66}; 67 68/* General Purpose Timer (GPT) registers */ 69struct gpt_regs { 70 u32 ctrl; /* control */ 71 u32 pre; /* prescaler */ 72 u32 stat; /* status */ 73 u32 intr; /* interrupt */ 74 u32 cmp[3]; /* output compare 1-3 */ 75 u32 capt[2]; /* input capture 1-2 */ 76 u32 counter; /* counter */ 77}; 78 79/* Watchdog Timer (WDOG) registers */ 80struct wdog_regs { 81 u16 wcr; /* Control */ 82 u16 wsr; /* Service */ 83 u16 wrsr; /* Reset Status */ 84 u16 wicr; /* Interrupt Control */ 85 u16 wmcr; /* Misc Control */ 86}; 87 88/* IIM control registers */ 89struct iim_regs { 90 u32 iim_stat; 91 u32 iim_statm; 92 u32 iim_err; 93 u32 iim_emask; 94 u32 iim_fctl; 95 u32 iim_ua; 96 u32 iim_la; 97 u32 iim_sdat; 98 u32 iim_prev; 99 u32 iim_srev; 100 u32 iim_prg_p; 101 u32 iim_scs0; 102 u32 iim_scs1; 103 u32 iim_scs2; 104 u32 iim_scs3; 105 u32 res1[0x1f1]; 106 struct fuse_bank { 107 u32 fuse_regs[0x20]; 108 u32 fuse_rsvd[0xe0]; 109 } bank[3]; 110}; 111 112struct fuse_bank0_regs { 113 u32 fuse0_7[8]; 114 u32 uid[8]; 115 u32 fuse16_25[0xa]; 116 u32 mac_addr[6]; 117}; 118 119struct fuse_bank1_regs { 120 u32 fuse0_21[0x16]; 121 u32 usr5; 122 u32 fuse23_29[7]; 123 u32 usr6[2]; 124}; 125 126/* Multi-Layer AHB Crossbar Switch (MAX) registers */ 127struct max_regs { 128 u32 mpr0; 129 u32 pad00[3]; 130 u32 sgpcr0; 131 u32 pad01[59]; 132 u32 mpr1; 133 u32 pad02[3]; 134 u32 sgpcr1; 135 u32 pad03[59]; 136 u32 mpr2; 137 u32 pad04[3]; 138 u32 sgpcr2; 139 u32 pad05[59]; 140 u32 mpr3; 141 u32 pad06[3]; 142 u32 sgpcr3; 143 u32 pad07[59]; 144 u32 mpr4; 145 u32 pad08[3]; 146 u32 sgpcr4; 147 u32 pad09[251]; 148 u32 mgpcr0; 149 u32 pad10[63]; 150 u32 mgpcr1; 151 u32 pad11[63]; 152 u32 mgpcr2; 153 u32 pad12[63]; 154 u32 mgpcr3; 155 u32 pad13[63]; 156 u32 mgpcr4; 157}; 158 159/* AHB <-> IP-Bus Interface (AIPS) */ 160struct aips_regs { 161 u32 mpr_0_7; 162 u32 mpr_8_15; 163}; 164 165#endif 166 167#define ARCH_MXC 168 169/* AIPS 1 */ 170#define IMX_AIPS1_BASE (0x43F00000) 171#define IMX_MAX_BASE (0x43F04000) 172#define IMX_CLKCTL_BASE (0x43F08000) 173#define IMX_ETB_SLOT4_BASE (0x43F0C000) 174#define IMX_ETB_SLOT5_BASE (0x43F10000) 175#define IMX_ECT_CTIO_BASE (0x43F18000) 176#define IMX_I2C_BASE (0x43F80000) 177#define IMX_I2C3_BASE (0x43F84000) 178#define IMX_CAN1_BASE (0x43F88000) 179#define IMX_CAN2_BASE (0x43F8C000) 180#define UART1_BASE (0x43F90000) 181#define UART2_BASE (0x43F94000) 182#define IMX_I2C2_BASE (0x43F98000) 183#define IMX_OWIRE_BASE (0x43F9C000) 184#define IMX_CSPI1_BASE (0x43FA4000) 185#define IMX_KPP_BASE (0x43FA8000) 186#define IMX_IOPADMUX_BASE (0x43FAC000) 187#define IOMUXC_BASE_ADDR IMX_IOPADMUX_BASE 188#define IMX_IOPADCTL_BASE (0x43FAC22C) 189#define IMX_IOPADGRPCTL_BASE (0x43FAC418) 190#define IMX_IOPADINPUTSEL_BASE (0x43FAC460) 191#define IMX_AUDMUX_BASE (0x43FB0000) 192#define IMX_ECT_IP1_BASE (0x43FB8000) 193#define IMX_ECT_IP2_BASE (0x43FBC000) 194 195/* SPBA */ 196#define IMX_SPBA_BASE (0x50000000) 197#define IMX_CSPI3_BASE (0x50004000) 198#define UART4_BASE (0x50008000) 199#define UART3_BASE (0x5000C000) 200#define IMX_CSPI2_BASE (0x50010000) 201#define IMX_SSI2_BASE (0x50014000) 202#define IMX_ESAI_BASE (0x50018000) 203#define IMX_ATA_DMA_BASE (0x50020000) 204#define IMX_SIM1_BASE (0x50024000) 205#define IMX_SIM2_BASE (0x50028000) 206#define UART5_BASE (0x5002C000) 207#define IMX_TSC_BASE (0x50030000) 208#define IMX_SSI1_BASE (0x50034000) 209#define IMX_FEC_BASE (0x50038000) 210#define IMX_SPBA_CTRL_BASE (0x5003C000) 211 212/* AIPS 2 */ 213#define IMX_AIPS2_BASE (0x53F00000) 214#define IMX_CCM_BASE (0x53F80000) 215#define IMX_GPT4_BASE (0x53F84000) 216#define IMX_GPT3_BASE (0x53F88000) 217#define IMX_GPT2_BASE (0x53F8C000) 218#define IMX_GPT1_BASE (0x53F90000) 219#define IMX_EPIT1_BASE (0x53F94000) 220#define IMX_EPIT2_BASE (0x53F98000) 221#define IMX_GPIO4_BASE (0x53F9C000) 222#define IMX_PWM2_BASE (0x53FA0000) 223#define IMX_GPIO3_BASE (0x53FA4000) 224#define IMX_PWM3_BASE (0x53FA8000) 225#define IMX_SCC_BASE (0x53FAC000) 226#define IMX_SCM_BASE (0x53FAE000) 227#define IMX_SMN_BASE (0x53FAF000) 228#define IMX_RNGD_BASE (0x53FB0000) 229#define IMX_MMC_SDHC1_BASE (0x53FB4000) 230#define IMX_MMC_SDHC2_BASE (0x53FB8000) 231#define IMX_LCDC_BASE (0x53FBC000) 232#define IMX_SLCDC_BASE (0x53FC0000) 233#define IMX_PWM4_BASE (0x53FC8000) 234#define IMX_GPIO1_BASE (0x53FCC000) 235#define IMX_GPIO2_BASE (0x53FD0000) 236#define IMX_SDMA_BASE (0x53FD4000) 237#define IMX_WDT_BASE (0x53FDC000) 238#define IMX_PWM1_BASE (0x53FE0000) 239#define IMX_RTIC_BASE (0x53FEC000) 240#define IMX_IIM_BASE (0x53FF0000) 241#define IIM_BASE_ADDR IMX_IIM_BASE 242#define IMX_USB_BASE (0x53FF4000) 243#define IMX_USB_PORT_OFFSET 0x200 244#define IMX_CSI_BASE (0x53FF8000) 245#define IMX_DRYICE_BASE (0x53FFC000) 246 247#define IMX_ARM926_ROMPATCH (0x60000000) 248#define IMX_ARM926_ASIC (0x68000000) 249 250/* 128K Internal Static RAM */ 251#define IMX_RAM_BASE (0x78000000) 252#define IMX_RAM_SIZE (128 * 1024) 253 254/* SDRAM BANKS */ 255#define IMX_SDRAM_BANK0_BASE (0x80000000) 256#define IMX_SDRAM_BANK1_BASE (0x90000000) 257 258#define IMX_WEIM_CS0 (0xA0000000) 259#define IMX_WEIM_CS1 (0xA8000000) 260#define IMX_WEIM_CS2 (0xB0000000) 261#define IMX_WEIM_CS3 (0xB2000000) 262#define IMX_WEIM_CS4 (0xB4000000) 263#define IMX_ESDRAMC_BASE (0xB8001000) 264#define IMX_WEIM_CTRL_BASE (0xB8002000) 265#define IMX_M3IF_CTRL_BASE (0xB8003000) 266#define IMX_EMI_CTRL_BASE (0xB8004000) 267 268/* NAND Flash Controller */ 269#define IMX_NFC_BASE (0xBB000000) 270#define NFC_BASE_ADDR IMX_NFC_BASE 271 272/* CCM bitfields */ 273#define CCM_PLL_MFI_SHIFT 10 274#define CCM_PLL_MFI_MASK 0xf 275#define CCM_PLL_MFN_SHIFT 0 276#define CCM_PLL_MFN_MASK 0x3ff 277#define CCM_PLL_MFD_SHIFT 16 278#define CCM_PLL_MFD_MASK 0x3ff 279#define CCM_PLL_PD_SHIFT 26 280#define CCM_PLL_PD_MASK 0xf 281#define CCM_CCTL_ARM_DIV_SHIFT 30 282#define CCM_CCTL_ARM_DIV_MASK 3 283#define CCM_CCTL_AHB_DIV_SHIFT 28 284#define CCM_CCTL_AHB_DIV_MASK 3 285#define CCM_CCTL_ARM_SRC (1 << 14) 286#define CCM_CGR1_GPT1 (1 << 19) 287#define CCM_PERCLK_REG(clk) (clk / 4) 288#define CCM_PERCLK_SHIFT(clk) (8 * (clk % 4)) 289#define CCM_PERCLK_MASK 0x3f 290#define CCM_RCSR_NF_16BIT_SEL (1 << 14) 291#define CCM_RCSR_NF_PS(v) ((v >> 26) & 3) 292 293/* ESDRAM Controller register bitfields */ 294#define ESDCTL_PRCT(x) (((x) & 0x3f) << 0) 295#define ESDCTL_BL (1 << 7) 296#define ESDCTL_FP (1 << 8) 297#define ESDCTL_PWDT(x) (((x) & 3) << 10) 298#define ESDCTL_SREFR(x) (((x) & 7) << 13) 299#define ESDCTL_DSIZ_16_UPPER (0 << 16) 300#define ESDCTL_DSIZ_16_LOWER (1 << 16) 301#define ESDCTL_DSIZ_32 (2 << 16) 302#define ESDCTL_COL8 (0 << 20) 303#define ESDCTL_COL9 (1 << 20) 304#define ESDCTL_COL10 (2 << 20) 305#define ESDCTL_ROW11 (0 << 24) 306#define ESDCTL_ROW12 (1 << 24) 307#define ESDCTL_ROW13 (2 << 24) 308#define ESDCTL_ROW14 (3 << 24) 309#define ESDCTL_ROW15 (4 << 24) 310#define ESDCTL_SP (1 << 27) 311#define ESDCTL_SMODE_NORMAL (0 << 28) 312#define ESDCTL_SMODE_PRECHARGE (1 << 28) 313#define ESDCTL_SMODE_AUTO_REF (2 << 28) 314#define ESDCTL_SMODE_LOAD_MODE (3 << 28) 315#define ESDCTL_SMODE_MAN_REF (4 << 28) 316#define ESDCTL_SDE (1 << 31) 317 318#define ESDCFG_TRC(x) (((x) & 0xf) << 0) 319#define ESDCFG_TRCD(x) (((x) & 0x7) << 4) 320#define ESDCFG_TCAS(x) (((x) & 0x3) << 8) 321#define ESDCFG_TRRD(x) (((x) & 0x3) << 10) 322#define ESDCFG_TRAS(x) (((x) & 0x7) << 12) 323#define ESDCFG_TWR (1 << 15) 324#define ESDCFG_TMRD(x) (((x) & 0x3) << 16) 325#define ESDCFG_TRP(x) (((x) & 0x3) << 18) 326#define ESDCFG_TWTR (1 << 20) 327#define ESDCFG_TXP(x) (((x) & 0x3) << 21) 328 329#define ESDMISC_RST (1 << 1) 330#define ESDMISC_MDDREN (1 << 2) 331#define ESDMISC_MDDR_DL_RST (1 << 3) 332#define ESDMISC_MDDR_MDIS (1 << 4) 333#define ESDMISC_LHD (1 << 5) 334#define ESDMISC_MA10_SHARE (1 << 6) 335#define ESDMISC_SDRAM_RDY (1 << 31) 336 337/* GPT bits */ 338#define GPT_CTRL_SWR (1 << 15) /* Software reset */ 339#define GPT_CTRL_FRR (1 << 9) /* Freerun / restart */ 340#define GPT_CTRL_CLKSOURCE_32 (4 << 6) /* Clock source */ 341#define GPT_CTRL_TEN 1 /* Timer enable */ 342 343/* WDOG enable */ 344#define WCR_WDE 0x04 345#define WSR_UNLOCK1 0x5555 346#define WSR_UNLOCK2 0xAAAA 347 348/* Names used in GPIO driver */ 349#define GPIO1_BASE_ADDR IMX_GPIO1_BASE 350#define GPIO2_BASE_ADDR IMX_GPIO2_BASE 351#define GPIO3_BASE_ADDR IMX_GPIO3_BASE 352#define GPIO4_BASE_ADDR IMX_GPIO4_BASE 353 354#define CHIP_REV_1_0 0x10 355#define CHIP_REV_1_1 0x11 356#define CHIP_REV_1_2 0x12 357 358#endif /* _IMX_REGS_H */ 359