LXR uboot/arch/powerpc/cpu/mpc5xx/start.S

   1/*
   2 *  Copyright (C) 1998  Dan Malek <dmalek@jlc.net>
   3 *  Copyright (C) 1999  Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
   4 *  Copyright (C) 2000, 2001, 2002 Wolfgang Denk <wd@denx.de>
   5 *  Copyright (C) 2003  Martin Winistoerfer, martinwinistoerfer@gmx.ch.
   6 *
   7 * SPDX-License-Identifier:     GPL-2.0+
   8 */
   9
  10/*
  11 * File:                start.S
  12 *
  13 * Discription:         startup code
  14 *
  15 */
  16
  17#include <asm-offsets.h>
  18#include <config.h>
  19#include <mpc5xx.h>
  20#include <version.h>
  21
  22#define CONFIG_5xx 1            /* needed for Linux kernel header files */
  23#define _LINUX_CONFIG_H 1       /* avoid reading Linux autoconf.h file  */
  24
  25#include <ppc_asm.tmpl>
  26#include <ppc_defs.h>
  27
  28#include <asm/processor.h>
  29#include <asm/u-boot.h>
  30
  31/* We don't have a MMU.
  32*/
  33#undef  MSR_KERNEL
  34#define MSR_KERNEL ( MSR_ME | MSR_RI )          /* Machine Check and Recoverable Interr. */
  35
  36/*
  37 * Set up GOT: Global Offset Table
  38 *
  39 * Use r12 to access the GOT
  40 */
  41        START_GOT
  42        GOT_ENTRY(_GOT2_TABLE_)
  43        GOT_ENTRY(_FIXUP_TABLE_)
  44
  45        GOT_ENTRY(_start)
  46        GOT_ENTRY(_start_of_vectors)
  47        GOT_ENTRY(_end_of_vectors)
  48        GOT_ENTRY(transfer_to_handler)
  49
  50        GOT_ENTRY(__init_end)
  51        GOT_ENTRY(__bss_end)
  52        GOT_ENTRY(__bss_start)
  53        END_GOT
  54
  55/*
  56 * r3 - 1st arg to board_init(): IMMP pointer
  57 * r4 - 2nd arg to board_init(): boot flag
  58 */
  59        .text
  60        .long   0x27051956                      /* U-Boot Magic Number */
  61        .globl  version_string
  62version_string:
  63        .ascii U_BOOT_VERSION_STRING, "\0"
  64
  65        . = EXC_OFF_SYS_RESET
  66        .globl  _start
  67_start:
  68        mfspr   r3, 638
  69        li      r4, CONFIG_SYS_ISB                      /* Set ISB bit */
  70        or      r3, r3, r4
  71        mtspr   638, r3
  72
  73        /* Initialize machine status; enable machine check interrupt            */
  74        /*----------------------------------------------------------------------*/
  75        li      r3, MSR_KERNEL                  /* Set ME, RI flags */
  76        mtmsr   r3
  77        mtspr   SRR1, r3                        /* Make SRR1 match MSR */
  78
  79        /* Initialize debug port registers                                      */
  80        /*----------------------------------------------------------------------*/
  81        xor     r0, r0, r0                      /* Clear R0 */
  82        mtspr   LCTRL1, r0                      /* Initialize debug port regs */
  83        mtspr   LCTRL2, r0
  84        mtspr   COUNTA, r0
  85        mtspr   COUNTB, r0
  86
  87#if defined(CONFIG_PATI)
  88        /* the external flash access on PATI fails if programming the PLL to 40MHz.
  89         * Copy the PLL programming code to the internal RAM and execute it
  90         *----------------------------------------------------------------------*/
  91        lis     r3, CONFIG_SYS_MONITOR_BASE@h
  92        ori     r3, r3, CONFIG_SYS_MONITOR_BASE@l
  93        addi    r3, r3, pll_prog_code_start - _start + EXC_OFF_SYS_RESET
  94
  95        lis     r4, CONFIG_SYS_INIT_RAM_ADDR@h
  96        ori     r4, r4, CONFIG_SYS_INIT_RAM_ADDR@l
  97        mtlr    r4
  98        addis   r5,0,0x0
  99        ori     r5,r5,((pll_prog_code_end - pll_prog_code_start) >>2)
 100        mtctr   r5
 101        addi    r3, r3, -4
 102        addi    r4, r4, -4
 1030:
 104        lwzu    r0,4(r3)
 105        stwu    r0,4(r4)
 106        bdnz    0b                /* copy loop */
 107        blrl
 108#endif
 109
 110        /*
 111         * Calculate absolute address in FLASH and jump there
 112         *----------------------------------------------------------------------*/
 113
 114        lis     r3, CONFIG_SYS_MONITOR_BASE@h
 115        ori     r3, r3, CONFIG_SYS_MONITOR_BASE@l
 116        addi    r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
 117        mtlr    r3
 118        blr
 119
 120in_flash:
 121
 122        /* Initialize some SPRs that are hard to access from C                  */
 123        /*----------------------------------------------------------------------*/
 124
 125        lis     r3, CONFIG_SYS_IMMR@h                   /* Pass IMMR as arg1 to C routine */
 126        lis     r2, CONFIG_SYS_INIT_SP_ADDR@h
 127        ori     r1, r2, CONFIG_SYS_INIT_SP_ADDR@l       /* Set up the stack in internal SRAM */
 128        /* Note: R0 is still 0 here */
 129        stwu    r0, -4(r1)                      /* Clear final stack frame so that      */
 130        stwu    r0, -4(r1)                      /* stack backtraces terminate cleanly   */
 131
 132        /*
 133         * Disable serialized ifetch and show cycles
 134         * (i.e. set processor to normal mode) for maximum
 135         * performance.
 136         */
 137
 138        li      r2, 0x0007
 139        mtspr   ICTRL, r2
 140
 141        /* Set up debug mode entry */
 142
 143        lis     r2, CONFIG_SYS_DER@h
 144        ori     r2, r2, CONFIG_SYS_DER@l
 145        mtspr   DER, r2
 146
 147        /* Let the C-code set up the rest                                       */
 148        /*                                                                      */
 149        /* Be careful to keep code relocatable !                                */
 150        /*----------------------------------------------------------------------*/
 151
 152        GET_GOT                 /* initialize GOT access                        */
 153
 154        /* r3: IMMR */
 155        bl      cpu_init_f      /* run low-level CPU init code     (from Flash) */
 156
 157        bl      board_init_f    /* run 1st part of board init code (from Flash) */
 158
 159        /* NOTREACHED - board_init_f() does not return */
 160
 161
 162        .globl  _start_of_vectors
 163_start_of_vectors:
 164
 165/* Machine check */
 166        STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
 167
 168/* Data Storage exception.  "Never" generated on the 860. */
 169        STD_EXCEPTION(0x300, DataStorage, UnknownException)
 170
 171/* Instruction Storage exception.  "Never" generated on the 860. */
 172        STD_EXCEPTION(0x400, InstStorage, UnknownException)
 173
 174/* External Interrupt exception. */
 175        STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
 176
 177/* Alignment exception. */
 178        . = 0x600
 179Alignment:
 180        EXCEPTION_PROLOG(SRR0, SRR1)
 181        mfspr   r4,DAR
 182        stw     r4,_DAR(r21)
 183        mfspr   r5,DSISR
 184        stw     r5,_DSISR(r21)
 185        addi    r3,r1,STACK_FRAME_OVERHEAD
 186        EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
 187
 188/* Program check exception */
 189        . = 0x700
 190ProgramCheck:
 191        EXCEPTION_PROLOG(SRR0, SRR1)
 192        addi    r3,r1,STACK_FRAME_OVERHEAD
 193        EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
 194                MSR_KERNEL, COPY_EE)
 195
 196        /* FPU on MPC5xx available. We will use it later.
 197        */
 198        STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
 199
 200        /* I guess we could implement decrementer, and may have
 201         * to someday for timekeeping.
 202         */
 203        STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
 204        STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
 205        STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
 206        STD_EXCEPTION(0xc00, SystemCall, UnknownException)
 207        STD_EXCEPTION(0xd00, SingleStep, UnknownException)
 208
 209        STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
 210        STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
 211
 212        /* On the MPC8xx, this is a software emulation interrupt.  It occurs
 213         * for all unimplemented and illegal instructions.
 214         */
 215        STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
 216        STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
 217        STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
 218        STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
 219        STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
 220
 221        STD_EXCEPTION(0x1500, Reserved5, UnknownException)
 222        STD_EXCEPTION(0x1600, Reserved6, UnknownException)
 223        STD_EXCEPTION(0x1700, Reserved7, UnknownException)
 224        STD_EXCEPTION(0x1800, Reserved8, UnknownException)
 225        STD_EXCEPTION(0x1900, Reserved9, UnknownException)
 226        STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
 227        STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
 228
 229        STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
 230        STD_EXCEPTION(0x1d00, InstructionBreakpoint, DebugException)
 231        STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
 232        STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
 233
 234
 235        .globl  _end_of_vectors
 236_end_of_vectors:
 237
 238
 239        . = 0x2000
 240
 241/*
 242 * This code finishes saving the registers to the exception frame
 243 * and jumps to the appropriate handler for the exception.
 244 * Register r21 is pointer into trap frame, r1 has new stack pointer.
 245 */
 246        .globl  transfer_to_handler
 247transfer_to_handler:
 248        stw     r22,_NIP(r21)
 249        lis     r22,MSR_POW@h
 250        andc    r23,r23,r22
 251        stw     r23,_MSR(r21)
 252        SAVE_GPR(7, r21)
 253        SAVE_4GPRS(8, r21)
 254        SAVE_8GPRS(12, r21)
 255        SAVE_8GPRS(24, r21)
 256        mflr    r23
 257        andi.   r24,r23,0x3f00          /* get vector offset */
 258        stw     r24,TRAP(r21)
 259        li      r22,0
 260        stw     r22,RESULT(r21)
 261        mtspr   SPRG2,r22               /* r1 is now kernel sp */
 262        lwz     r24,0(r23)              /* virtual address of handler */
 263        lwz     r23,4(r23)              /* where to go when done */
 264        mtspr   SRR0,r24
 265        mtspr   SRR1,r20
 266        mtlr    r23
 267        SYNC
 268        rfi                             /* jump to handler, enable MMU */
 269
 270int_return:
 271        mfmsr   r28                     /* Disable interrupts */
 272        li      r4,0
 273        ori     r4,r4,MSR_EE
 274        andc    r28,r28,r4
 275        SYNC                            /* Some chip revs need this... */
 276        mtmsr   r28
 277        SYNC
 278        lwz     r2,_CTR(r1)
 279        lwz     r0,_LINK(r1)
 280        mtctr   r2
 281        mtlr    r0
 282        lwz     r2,_XER(r1)
 283        lwz     r0,_CCR(r1)
 284        mtspr   XER,r2
 285        mtcrf   0xFF,r0
 286        REST_10GPRS(3, r1)
 287        REST_10GPRS(13, r1)
 288        REST_8GPRS(23, r1)
 289        REST_GPR(31, r1)
 290        lwz     r2,_NIP(r1)             /* Restore environment */
 291        lwz     r0,_MSR(r1)
 292        mtspr   SRR0,r2
 293        mtspr   SRR1,r0
 294        lwz     r0,GPR0(r1)
 295        lwz     r2,GPR2(r1)
 296        lwz     r1,GPR1(r1)
 297        SYNC
 298        rfi
 299
 300
 301/*
 302 * unsigned int get_immr (unsigned int mask)
 303 *
 304 * return (mask ? (IMMR & mask) : IMMR);
 305 */
 306        .globl  get_immr
 307get_immr:
 308        mr      r4,r3           /* save mask */
 309        mfspr   r3, IMMR        /* IMMR */
 310        cmpwi   0,r4,0          /* mask != 0 ? */
 311        beq     4f
 312        and     r3,r3,r4        /* IMMR & mask */
 3134:
 314        blr
 315
 316        .globl get_pvr
 317get_pvr:
 318        mfspr   r3, PVR
 319        blr
 320
 321
 322/*------------------------------------------------------------------------------*/
 323
 324/*
 325 * void relocate_code (addr_sp, gd, addr_moni)
 326 *
 327 * This "function" does not return, instead it continues in RAM
 328 * after relocating the monitor code.
 329 *
 330 * r3 = dest
 331 * r4 = src
 332 * r5 = length in bytes
 333 * r6 = cachelinesize
 334 */
 335        .globl  relocate_code
 336relocate_code:
 337        mr      r1,  r3         /* Set new stack pointer in SRAM        */
 338        mr      r9,  r4         /* Save copy of global data pointer in SRAM */
 339        mr      r10, r5         /* Save copy of monitor destination Address in SRAM */
 340
 341        GET_GOT
 342        mr      r3,  r5                         /* Destination Address  */
 343        lis     r4, CONFIG_SYS_MONITOR_BASE@h           /* Source      Address  */
 344        ori     r4, r4, CONFIG_SYS_MONITOR_BASE@l
 345        lwz     r5, GOT(__init_end)
 346        sub     r5, r5, r4
 347
 348        /*
 349         * Fix GOT pointer:
 350         *
 351         * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
 352         *
 353         * Offset:
 354         */
 355        sub     r15, r10, r4
 356
 357        /* First our own GOT */
 358        add     r12, r12, r15
 359        /* the the one used by the C code */
 360        add     r30, r30, r15
 361
 362        /*
 363         * Now relocate code
 364         */
 365
 366        cmplw   cr1,r3,r4
 367        addi    r0,r5,3
 368        srwi.   r0,r0,2
 369        beq     cr1,4f          /* In place copy is not necessary       */
 370        beq     4f              /* Protect against 0 count              */
 371        mtctr   r0
 372        bge     cr1,2f
 373
 374        la      r8,-4(r4)
 375        la      r7,-4(r3)
 3761:      lwzu    r0,4(r8)
 377        stwu    r0,4(r7)
 378        bdnz    1b
 379        b       4f
 380
 3812:      slwi    r0,r0,2
 382        add     r8,r4,r0
 383        add     r7,r3,r0
 3843:      lwzu    r0,-4(r8)
 385        stwu    r0,-4(r7)
 386        bdnz    3b
 387
 3884:      sync
 389        isync
 390
 391/*
 392 * We are done. Do not return, instead branch to second part of board
 393 * initialization, now running from RAM.
 394 */
 395
 396        addi    r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
 397        mtlr    r0
 398        blr
 399
 400in_ram:
 401
 402        /*
 403         * Relocation Function, r12 point to got2+0x8000
 404         *
 405         * Adjust got2 pointers, no need to check for 0, this code
 406         * already puts a few entries in the table.
 407         */
 408        li      r0,__got2_entries@sectoff@l
 409        la      r3,GOT(_GOT2_TABLE_)
 410        lwz     r11,GOT(_GOT2_TABLE_)
 411        mtctr   r0
 412        sub     r11,r3,r11
 413        addi    r3,r3,-4
 4141:      lwzu    r0,4(r3)
 415        cmpwi   r0,0
 416        beq-    2f
 417        add     r0,r0,r11
 418        stw     r0,0(r3)
 4192:      bdnz    1b
 420
 421        /*
 422         * Now adjust the fixups and the pointers to the fixups
 423         * in case we need to move ourselves again.
 424         */
 425        li      r0,__fixup_entries@sectoff@l
 426        lwz     r3,GOT(_FIXUP_TABLE_)
 427        cmpwi   r0,0
 428        mtctr   r0
 429        addi    r3,r3,-4
 430        beq     4f
 4313:      lwzu    r4,4(r3)
 432        lwzux   r0,r4,r11
 433        cmpwi   r0,0
 434        add     r0,r0,r11
 435        stw     r4,0(r3)
 436        beq-    5f
 437        stw     r0,0(r4)
 4385:      bdnz    3b
 4394:
 440clear_bss:
 441        /*
 442         * Now clear BSS segment
 443         */
 444        lwz     r3,GOT(__bss_start)
 445        lwz     r4,GOT(__bss_end)
 446        cmplw   0, r3, r4
 447        beq     6f
 448
 449        li      r0, 0
 4505:
 451        stw     r0, 0(r3)
 452        addi    r3, r3, 4
 453        cmplw   0, r3, r4
 454        bne     5b
 4556:
 456
 457        mr      r3, r9          /* Global Data pointer          */
 458        mr      r4, r10         /* Destination Address          */
 459        bl      board_init_r
 460
 461        /*
 462         * Copy exception vector code to low memory
 463         *
 464         * r3: dest_addr
 465         * r7: source address, r8: end address, r9: target address
 466         */
 467        .globl  trap_init
 468trap_init:
 469        mflr    r4                      /* save link register           */
 470        GET_GOT
 471        lwz     r7, GOT(_start)
 472        lwz     r8, GOT(_end_of_vectors)
 473
 474        li      r9, 0x100               /* reset vector always at 0x100 */
 475
 476        cmplw   0, r7, r8
 477        bgelr                           /* return if r7>=r8 - just in case */
 4781:
 479        lwz     r0, 0(r7)
 480        stw     r0, 0(r9)
 481        addi    r7, r7, 4
 482        addi    r9, r9, 4
 483        cmplw   0, r7, r8
 484        bne     1b
 485
 486        /*
 487         * relocate `hdlr' and `int_return' entries
 488         */
 489        li      r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
 490        li      r8, Alignment - _start + EXC_OFF_SYS_RESET
 4912:
 492        bl      trap_reloc
 493        addi    r7, r7, 0x100           /* next exception vector        */
 494        cmplw   0, r7, r8
 495        blt     2b
 496
 497        li      r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
 498        bl      trap_reloc
 499
 500        li      r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
 501        bl      trap_reloc
 502
 503        li      r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
 504        li      r8, SystemCall - _start + EXC_OFF_SYS_RESET
 5053:
 506        bl      trap_reloc
 507        addi    r7, r7, 0x100           /* next exception vector        */
 508        cmplw   0, r7, r8
 509        blt     3b
 510
 511        li      r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
 512        li      r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
 5134:
 514        bl      trap_reloc
 515        addi    r7, r7, 0x100           /* next exception vector        */
 516        cmplw   0, r7, r8
 517        blt     4b
 518
 519        mtlr    r4                      /* restore link register        */
 520        blr
 521
 522#if defined(CONFIG_PATI)
 523/* Program the PLL */
 524pll_prog_code_start:
 525        lis     r4, (CONFIG_SYS_IMMR + 0x002fc384)@h
 526        ori     r4, r4, (CONFIG_SYS_IMMR + 0x002fc384)@l
 527        lis     r3, (0x55ccaa33)@h
 528        ori     r3, r3, (0x55ccaa33)@l
 529        stw     r3, 0(r4)
 530        lis     r4, (CONFIG_SYS_IMMR + 0x002fc284)@h
 531        ori     r4, r4, (CONFIG_SYS_IMMR + 0x002fc284)@l
 532        lis     r3, CONFIG_SYS_PLPRCR@h
 533        ori     r3, r3, CONFIG_SYS_PLPRCR@l
 534        stw     r3, 0(r4)
 535        addis   r3,0,0x0
 536        ori     r3,r3,0xA000
 537        mtctr   r3
 538..spinlp:
 539  bdnz    ..spinlp                /* spin loop */
 540        blr
 541pll_prog_code_end:
 542        nop
 543        blr
 544#endif
 545