LXR uboot/arch/sh/cpu/sh2/cpu.c

   1/*
   2 * Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
   3 * Copyright (C) 2008 Renesas Solutions Corp.
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 */
   7
   8#include <common.h>
   9#include <command.h>
  10#include <asm/processor.h>
  11#include <asm/io.h>
  12
  13#define STBCR4      0xFFFE040C
  14#define cmt_clock_enable() do {\
  15                writeb(readb(STBCR4) & ~0x04, STBCR4);\
  16        } while (0)
  17#define scif0_enable() do {\
  18                writeb(readb(STBCR4) & ~0x80, STBCR4);\
  19        } while (0)
  20#define scif3_enable() do {\
  21                writeb(readb(STBCR4) & ~0x10, STBCR4);\
  22        } while (0)
  23
  24int checkcpu(void)
  25{
  26        puts("CPU: SH2\n");
  27        return 0;
  28}
  29
  30int cpu_init(void)
  31{
  32        /* SCIF enable */
  33#if defined(CONFIG_CONS_SCIF3)
  34        scif3_enable();
  35#else
  36        scif0_enable();
  37#endif
  38        /* CMT clock enable */
  39        cmt_clock_enable() ;
  40        return 0;
  41}
  42
  43int cleanup_before_linux(void)
  44{
  45        disable_interrupts();
  46        return 0;
  47}
  48
  49int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  50{
  51        disable_interrupts();
  52        reset_cpu(0);
  53        return 0;
  54}
  55
  56void flush_cache(unsigned long addr, unsigned long size)
  57{
  58
  59}
  60
  61void icache_enable(void)
  62{
  63}
  64
  65void icache_disable(void)
  66{
  67}
  68
  69int icache_status(void)
  70{
  71        return 0;
  72}
  73
  74void dcache_enable(void)
  75{
  76}
  77
  78void dcache_disable(void)
  79{
  80}
  81
  82int dcache_status(void)
  83{
  84        return 0;
  85}
  86