LXR uboot/board/cpc45/plx9030.c

   1/* Plx9030.c - system configuration module for PLX9030 PCI to Local Bus Bridge */
   2/*
   3 * (C) Copyright 2002-2003
   4 * Josef Wagner, MicroSys GmbH, wagner@microsys.de.
   5 *
   6 * SPDX-License-Identifier:     GPL-2.0+
   7 *   Date       Modification                                      by
   8 * -------      ----------------------------------------------    ---
   9 * 30sep02      converted from VxWorks to LINUX                   wa
  10*/
  11
  12
  13/*
  14DESCRIPTION
  15
  16This is the configuration module for the PLX9030 PCI to Local Bus Bridge.
  17It configures the Chip select lines for SRAM (CS0), ST16C552 (CS1,CS2), Display and local
  18registers (CS3) on CPC45.
  19*/
  20
  21/* includes */
  22
  23#include <common.h>
  24#include <malloc.h>
  25#include <net.h>
  26#include <asm/io.h>
  27#include <pci.h>
  28
  29/* imports */
  30
  31
  32/* defines */
  33#define PLX9030_VENDOR_ID       0x10B5
  34#define PLX9030_DEVICE_ID       0x9030
  35
  36#undef PLX_DEBUG
  37
  38/* PLX9030 register offsets  */
  39#define P9030_LAS0RR    0x00
  40#define P9030_LAS1RR    0x04
  41#define P9030_LAS2RR    0x08
  42#define P9030_LAS3RR    0x0c
  43#define P9030_EROMRR    0x10
  44#define P9030_LAS0BA    0x14
  45#define P9030_LAS1BA    0x18
  46#define P9030_LAS2BA    0x1c
  47#define P9030_LAS3BA    0x20
  48#define P9030_EROMBA    0x24
  49#define P9030_LAS0BRD   0x28
  50#define P9030_LAS1BRD   0x2c
  51#define P9030_LAS2BRD   0x30
  52#define P9030_LAS3BRD   0x34
  53#define P9030_EROMBRD   0x38
  54#define P9030_CS0BASE   0x3C
  55#define P9030_CS1BASE   0x40
  56#define P9030_CS2BASE   0x44
  57#define P9030_CS3BASE   0x48
  58#define P9030_INTCSR    0x4c
  59#define P9030_CNTRL     0x50
  60#define P9030_GPIOC     0x54
  61
  62/* typedefs */
  63
  64
  65/* locals */
  66
  67static struct pci_device_id supported[] = {
  68        { PLX9030_VENDOR_ID, PLX9030_DEVICE_ID },
  69        { }
  70};
  71
  72/* forward declarations */
  73void sysOutLong(ulong address, ulong value);
  74
  75
  76/***************************************************************************
  77*
  78* Plx9030Init - init CS0..CS3 for CPC45
  79*
  80*
  81* RETURNS: N/A
  82*/
  83
  84void Plx9030Init (void)
  85{
  86    pci_dev_t   devno;
  87    ulong       membaseCsr;       /* base address of device memory space */
  88    int         idx = 0;          /* general index */
  89
  90
  91    /* find plx9030 device */
  92
  93    if ((devno = pci_find_devices(supported, idx++)) < 0)
  94    {
  95        printf("No PLX9030 device found !!\n");
  96        return;
  97    }
  98
  99
 100#ifdef PLX_DEBUG
 101        printf("PLX 9030 device found ! devno = 0x%x\n",devno);
 102#endif
 103
 104        membaseCsr   = PCI_PLX9030_MEMADDR;
 105
 106        /* set base address */
 107        pci_write_config_dword(devno, PCI_BASE_ADDRESS_0, membaseCsr);
 108
 109        /* enable mapped memory and IO addresses */
 110        pci_write_config_dword(devno,
 111                               PCI_COMMAND,
 112                               PCI_COMMAND_MEMORY |
 113                               PCI_COMMAND_MASTER);
 114
 115
 116        /* configure GBIOC */
 117        sysOutLong((membaseCsr + P9030_GPIOC),   0x00000FC0);           /* CS2/CS3 enable */
 118
 119        /* configure CS0 (SRAM) */
 120        sysOutLong((membaseCsr + P9030_LAS0BA),  0x00000001);           /* enable space base */
 121        sysOutLong((membaseCsr + P9030_LAS0RR),  0x0FE00000);           /* 2 MByte */
 122        sysOutLong((membaseCsr + P9030_LAS0BRD), 0x51928900);           /* 4 wait states */
 123        sysOutLong((membaseCsr + P9030_CS0BASE), 0x00100001);           /* enable 2 MByte */
 124        /* remap CS0 (SRAM) */
 125        pci_write_config_dword(devno, PCI_BASE_ADDRESS_2, SRAM_BASE);
 126
 127        /* configure CS1 (ST16552 / CHAN A) */
 128        sysOutLong((membaseCsr + P9030_LAS1BA),  0x00400001);           /* enable space base */
 129        sysOutLong((membaseCsr + P9030_LAS1RR),  0x0FFFFF00);           /* 256 byte */
 130        sysOutLong((membaseCsr + P9030_LAS1BRD), 0x55122900);           /* 4 wait states */
 131        sysOutLong((membaseCsr + P9030_CS1BASE), 0x00400081);           /* enable 256 Byte */
 132        /* remap CS1 (ST16552 / CHAN A) */
 133        /* remap CS1 (ST16552 / CHAN A) */
 134        pci_write_config_dword(devno, PCI_BASE_ADDRESS_3, ST16552_A_BASE);
 135
 136        /* configure CS2 (ST16552 / CHAN B) */
 137        sysOutLong((membaseCsr + P9030_LAS2BA),  0x00800001);           /* enable space base */
 138        sysOutLong((membaseCsr + P9030_LAS2RR),  0x0FFFFF00);           /* 256 byte */
 139        sysOutLong((membaseCsr + P9030_LAS2BRD), 0x55122900);           /* 4 wait states */
 140        sysOutLong((membaseCsr + P9030_CS2BASE), 0x00800081);           /* enable 256 Byte */
 141        /* remap CS2 (ST16552 / CHAN B) */
 142        pci_write_config_dword(devno, PCI_BASE_ADDRESS_4, ST16552_B_BASE);
 143
 144        /* configure CS3 (BCSR) */
 145        sysOutLong((membaseCsr + P9030_LAS3BA),  0x00C00001);           /* enable space base */
 146        sysOutLong((membaseCsr + P9030_LAS3RR),  0x0FFFFF00);           /* 256 byte */
 147        sysOutLong((membaseCsr + P9030_LAS3BRD), 0x55357A80);           /* 9 wait states */
 148        sysOutLong((membaseCsr + P9030_CS3BASE), 0x00C00081);           /* enable 256 Byte */
 149        /* remap CS3 (DISPLAY and BCSR) */
 150        pci_write_config_dword(devno, PCI_BASE_ADDRESS_5, BCSR_BASE);
 151}
 152
 153void sysOutLong(ulong address, ulong value)
 154{
 155        *(ulong*)address = cpu_to_le32(value);
 156}
 157