LXR uboot/board/csb472/csb472.c

   1/*
   2 * (C) Copyright 2004
   3 * Tolunay Orkun, Nextio Inc., torkun@nextio.com
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 */
   7
   8#include <common.h>
   9#include <asm/processor.h>
  10#include <i2c.h>
  11#include <miiphy.h>
  12#include <asm/ppc4xx-emac.h>
  13
  14void sdram_init(void);
  15
  16/*
  17 * board_early_init_f: do early board initialization
  18 *
  19 */
  20int board_early_init_f(void)
  21{
  22   /*-------------------------------------------------------------------------+
  23   | Interrupt controller setup for the Walnut board.
  24   | Note: IRQ 0-15  405GP internally generated; active high; level sensitive
  25   |       IRQ 16    405GP internally generated; active low; level sensitive
  26   |       IRQ 17-24 RESERVED
  27   |       IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
  28   |       IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
  29   |       IRQ 27 (EXT IRQ 2) Not Used
  30   |       IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
  31   |       IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
  32   |       IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
  33   |       IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
  34   | Note for Walnut board:
  35   |       An interrupt taken for the FPGA (IRQ 25) indicates that either
  36   |       the Mouse, Keyboard, IRDA, or External Expansion caused the
  37   |       interrupt. The FPGA must be read to determine which device
  38   |       caused the interrupt. The default setting of the FPGA clears
  39   |
  40   +-------------------------------------------------------------------------*/
  41
  42        mtdcr (UIC0SR, 0xFFFFFFFF);   /* clear all ints */
  43        mtdcr (UIC0ER, 0x00000000);   /* disable all ints */
  44        mtdcr (UIC0CR, 0x00000000);   /* set all to be non-critical */
  45        mtdcr (UIC0PR, 0xFFFFFF83);   /* set int polarities */
  46        mtdcr (UIC0TR, 0x10000000);   /* set int trigger levels */
  47        mtdcr (UIC0VCR, 0x00000001);  /* set vect base=0,INT0 highest priority */
  48        mtdcr (UIC0SR, 0xFFFFFFFF);   /* clear all ints */
  49
  50        mtebc (EBC0_CFG, 0xa8400000);   /* EBC always driven */
  51
  52        return 0; /* success */
  53}
  54
  55/*
  56 * checkboard: identify/verify the board we are running
  57 *
  58 * Remark: we just assume it is correct board here!
  59 *
  60 */
  61int checkboard(void)
  62{
  63        printf("BOARD: Cogent CSB472\n");
  64
  65        return 0; /* success */
  66}
  67
  68/*
  69 * initram: Determine the size of mounted DRAM
  70 *
  71 * Size is determined by reading SDRAM configuration registers as
  72 * configured by initialization code
  73 *
  74 */
  75phys_size_t initdram (int board_type)
  76{
  77        ulong tot_size;
  78        ulong bank_size;
  79        ulong tmp;
  80
  81        /*
  82         * ToDo: Move the asm init routine sdram_init() to this C file,
  83         * or even better use some common ppc4xx code available
  84         * in arch/powerpc/cpu/ppc4xx
  85         */
  86        sdram_init();
  87
  88        tot_size = 0;
  89
  90        mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
  91        tmp = mfdcr (SDRAM0_CFGDATA);
  92        if (tmp & 0x00000001) {
  93                bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
  94                tot_size += bank_size;
  95        }
  96
  97        mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
  98        tmp = mfdcr (SDRAM0_CFGDATA);
  99        if (tmp & 0x00000001) {
 100                bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
 101                tot_size += bank_size;
 102        }
 103
 104        mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
 105        tmp = mfdcr (SDRAM0_CFGDATA);
 106        if (tmp & 0x00000001) {
 107                bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
 108                tot_size += bank_size;
 109        }
 110
 111        mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
 112        tmp = mfdcr (SDRAM0_CFGDATA);
 113        if (tmp & 0x00000001) {
 114                bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
 115                tot_size += bank_size;
 116        }
 117
 118        return tot_size;
 119}
 120
 121/*
 122 * last_stage_init: final configurations (such as PHY etc)
 123 *
 124 */
 125int last_stage_init(void)
 126{
 127        /* initialize the PHY */
 128        miiphy_reset("ppc_4xx_eth0", CONFIG_PHY_ADDR);
 129
 130        /* AUTO neg */
 131        miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, MII_BMCR,
 132                        BMCR_ANENABLE | BMCR_ANRESTART);
 133
 134        /* LEDs     */
 135        miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, MII_NWAYTEST, 0x0d08);
 136
 137        return 0; /* success */
 138}
 139