LXR uboot/board/esd/ash405/ash405.c

   1/*
   2 * (C) Copyright 2001-2003
   3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 */
   7
   8#include <common.h>
   9#include <asm/processor.h>
  10#include <asm/io.h>
  11#include <command.h>
  12#include <malloc.h>
  13
  14/* ------------------------------------------------------------------------- */
  15
  16#if 0
  17#define FPGA_DEBUG
  18#endif
  19
  20extern void lxt971_no_sleep(void);
  21
  22/* fpga configuration data - gzip compressed and generated by bin2c */
  23const unsigned char fpgadata[] =
  24{
  25#include "fpgadata.c"
  26};
  27
  28/*
  29 * include common fpga code (for esd boards)
  30 */
  31#include "../common/fpga.c"
  32
  33
  34int board_early_init_f (void)
  35{
  36        /*
  37         * IRQ 0-15  405GP internally generated; active high; level sensitive
  38         * IRQ 16    405GP internally generated; active low; level sensitive
  39         * IRQ 17-24 RESERVED
  40         * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
  41         * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
  42         * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
  43         * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
  44         * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
  45         * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
  46         * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
  47         */
  48        mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
  49        mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
  50        mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
  51        mtdcr(UIC0PR, 0xFFFFFF9F);       /* set int polarities */
  52        mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
  53        mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest priority*/
  54        mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
  55
  56        /*
  57         * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
  58         */
  59        mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
  60
  61        return 0;
  62}
  63
  64int misc_init_r (void)
  65{
  66        unsigned char *dst;
  67        ulong len = sizeof(fpgadata);
  68        int status;
  69        int index;
  70        int i;
  71
  72        dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
  73        if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
  74                printf ("GUNZIP ERROR - must RESET board to recover\n");
  75                do_reset (NULL, 0, 0, NULL);
  76        }
  77
  78        status = fpga_boot(dst, len);
  79        if (status != 0) {
  80                printf("\nFPGA: Booting failed ");
  81                switch (status) {
  82                case ERROR_FPGA_PRG_INIT_LOW:
  83                        printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
  84                        break;
  85                case ERROR_FPGA_PRG_INIT_HIGH:
  86                        printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
  87                        break;
  88                case ERROR_FPGA_PRG_DONE:
  89                        printf("(Timeout: DONE not high after programming FPGA)\n ");
  90                        break;
  91                }
  92
  93                /* display infos on fpgaimage */
  94                index = 15;
  95                for (i=0; i<4; i++) {
  96                        len = dst[index];
  97                        printf("FPGA: %s\n", &(dst[index+1]));
  98                        index += len+3;
  99                }
 100                putc ('\n');
 101                /* delayed reboot */
 102                for (i=20; i>0; i--) {
 103                        printf("Rebooting in %2d seconds \r",i);
 104                        for (index=0;index<1000;index++)
 105                                udelay(1000);
 106                }
 107                putc ('\n');
 108                do_reset(NULL, 0, 0, NULL);
 109        }
 110
 111        puts("FPGA:  ");
 112
 113        /* display infos on fpgaimage */
 114        index = 15;
 115        for (i=0; i<4; i++) {
 116                len = dst[index];
 117                printf("%s ", &(dst[index+1]));
 118                index += len+3;
 119        }
 120        putc ('\n');
 121
 122        free(dst);
 123
 124        /*
 125         * Reset FPGA via FPGA_DATA pin
 126         */
 127        SET_FPGA(FPGA_PRG | FPGA_CLK);
 128        udelay(1000); /* wait 1ms */
 129        SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
 130        udelay(1000); /* wait 1ms */
 131
 132        /*
 133         * Reset external DUARTs
 134         */
 135        out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_DUART_RST);
 136        udelay(10); /* wait 10us */
 137        out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_DUART_RST);
 138        udelay(1000); /* wait 1ms */
 139
 140        /*
 141         * Enable interrupts in exar duart mcr[3]
 142         */
 143        out_8((void *)(DUART0_BA + 4), 0x08);
 144        out_8((void *)(DUART1_BA + 4), 0x08);
 145        out_8((void *)(DUART2_BA + 4), 0x08);
 146        out_8((void *)(DUART3_BA + 4), 0x08);
 147
 148        return (0);
 149}
 150
 151
 152/*
 153 * Check Board Identity:
 154 */
 155
 156int checkboard (void)
 157{
 158        char str[64];
 159        int i = getenv_f("serial#", str, sizeof(str));
 160
 161        puts ("Board: ");
 162
 163        if (i == -1) {
 164                puts ("### No HW ID - assuming ASH405");
 165        } else {
 166                puts(str);
 167        }
 168
 169        putc ('\n');
 170
 171        return 0;
 172}
 173
 174void reset_phy(void)
 175{
 176#ifdef CONFIG_LXT971_NO_SLEEP
 177        /*
 178         * Disable sleep mode in LXT971
 179         */
 180        lxt971_no_sleep();
 181#endif
 182}
 183