LXR uboot/board/esd/cpci750/mpsc.c

   1/*
   2 * (C) Copyright 2001
   3 * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 */
   7
   8/*************************************************************************
   9 * changes for Marvell DB64360 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com>
  10 *
  11  ************************************************************************/
  12
  13/*
  14 * mpsc.c - driver for console over the MPSC.
  15 */
  16
  17
  18#include <common.h>
  19#include <config.h>
  20#include <asm/cache.h>
  21
  22#include <malloc.h>
  23#include "mpsc.h"
  24
  25#include "mv_regs.h"
  26
  27#include "../../Marvell/include/memory.h"
  28
  29DECLARE_GLOBAL_DATA_PTR;
  30
  31/* Define this if you wish to use the MPSC as a register based UART.
  32 * This will force the serial port to not use the SDMA engine at all.
  33 */
  34
  35#undef CONFIG_MPSC_DEBUG_PORT
  36
  37
  38int (*mpsc_putchar) (char ch) = mpsc_putchar_early;
  39char (*mpsc_getchar) (void) = mpsc_getchar_debug;
  40int (*mpsc_test_char) (void) = mpsc_test_char_debug;
  41
  42
  43static volatile unsigned int *rx_desc_base = NULL;
  44static unsigned int rx_desc_index = 0;
  45static volatile unsigned int *tx_desc_base = NULL;
  46static unsigned int tx_desc_index = 0;
  47
  48/* local function declarations */
  49static int galmpsc_connect (int channel, int connect);
  50static int galmpsc_route_rx_clock (int channel, int brg);
  51static int galmpsc_route_tx_clock (int channel, int brg);
  52static int galmpsc_write_config_regs (int mpsc, int mode);
  53static int galmpsc_config_channel_regs (int mpsc);
  54static int galmpsc_set_char_length (int mpsc, int value);
  55static int galmpsc_set_stop_bit_length (int mpsc, int value);
  56static int galmpsc_set_parity (int mpsc, int value);
  57static int galmpsc_enter_hunt (int mpsc);
  58static int galmpsc_set_brkcnt (int mpsc, int value);
  59static int galmpsc_set_tcschar (int mpsc, int value);
  60static int galmpsc_set_snoop (int mpsc, int value);
  61static int galmpsc_shutdown (int mpsc);
  62
  63static int galsdma_set_RFT (int channel);
  64static int galsdma_set_SFM (int channel);
  65static int galsdma_set_rxle (int channel);
  66static int galsdma_set_txle (int channel);
  67static int galsdma_set_burstsize (int channel, unsigned int value);
  68static int galsdma_set_RC (int channel, unsigned int value);
  69
  70static int galbrg_set_CDV (int channel, int value);
  71static int galbrg_enable (int channel);
  72static int galbrg_disable (int channel);
  73static int galbrg_set_clksrc (int channel, int value);
  74static int galbrg_set_CUV (int channel, int value);
  75
  76static void galsdma_enable_rx (void);
  77static int galsdma_set_mem_space (unsigned int memSpace,
  78                                  unsigned int memSpaceTarget,
  79                                  unsigned int memSpaceAttr,
  80                                  unsigned int baseAddress,
  81                                  unsigned int size);
  82
  83
  84#define SOFTWARE_CACHE_MANAGEMENT
  85
  86#ifdef SOFTWARE_CACHE_MANAGEMENT
  87#define FLUSH_DCACHE(a,b)                if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));}
  88#define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));}
  89#define INVALIDATE_DCACHE(a,b)           if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));}
  90#else
  91#define FLUSH_DCACHE(a,b)
  92#define FLUSH_AND_INVALIDATE_DCACHE(a,b)
  93#define INVALIDATE_DCACHE(a,b)
  94#endif
  95
  96#ifdef CONFIG_MPSC_DEBUG_PORT
  97static void mpsc_debug_init (void)
  98{
  99
 100        volatile unsigned int temp;
 101
 102        /* Clear the CFR  (CHR4) */
 103        /* Write random 'Z' bit (bit 29) of CHR4 to enable debug uart *UNDOCUMENTED FEATURE* */
 104        temp = GTREGREAD (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP));
 105        temp &= 0xffffff00;
 106        temp |= BIT29;
 107        GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP),
 108                      temp);
 109
 110        /* Set the Valid bit 'V' (bit 12) and int generation bit 'INT' (bit 15) */
 111        temp = GTREGREAD (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP));
 112        temp |= (BIT12 | BIT15);
 113        GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP),
 114                      temp);
 115
 116        /* Set int mask */
 117        temp = GTREGREAD (GALMPSC_0_INT_MASK);
 118        temp |= BIT6;
 119        GT_REG_WRITE (GALMPSC_0_INT_MASK, temp);
 120}
 121#endif
 122
 123char mpsc_getchar_debug (void)
 124{
 125        volatile int temp;
 126        volatile unsigned int cause;
 127
 128        cause = GTREGREAD (GALMPSC_0_INT_CAUSE);
 129        while ((cause & BIT6) == 0) {
 130                cause = GTREGREAD (GALMPSC_0_INT_CAUSE);
 131        }
 132
 133        temp = GTREGREAD (GALMPSC_CHANNELREG_10 +
 134                          (CHANNEL * GALMPSC_REG_GAP));
 135        /* By writing 1's to the set bits, the register is cleared */
 136        GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (CHANNEL * GALMPSC_REG_GAP),
 137                      temp);
 138        GT_REG_WRITE (GALMPSC_0_INT_CAUSE, cause & ~BIT6);
 139        return (temp >> 16) & 0xff;
 140}
 141
 142/* special function for running out of flash.  doesn't modify any
 143 * global variables [josh] */
 144int mpsc_putchar_early (char ch)
 145{
 146        int mpsc = CHANNEL;
 147        int temp =
 148                GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
 149        galmpsc_set_tcschar (mpsc, ch);
 150        GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP),
 151                      temp | 0x200);
 152
 153#define MAGIC_FACTOR    (10*1000000)
 154
 155        udelay (MAGIC_FACTOR / gd->baudrate);
 156        return 0;
 157}
 158
 159/* This is used after relocation, see serial.c and mpsc_init2 */
 160static int mpsc_putchar_sdma (char ch)
 161{
 162        volatile unsigned int *p;
 163        unsigned int temp;
 164
 165
 166        /* align the descriptor */
 167        p = tx_desc_base;
 168        memset ((void *) p, 0, 8 * sizeof (unsigned int));
 169
 170        /* fill one 64 bit buffer */
 171        /* word swap, pad with 0 */
 172        p[4] = 0;               /* x */
 173        p[5] = (unsigned int) ch;       /* x */
 174
 175        /* CHANGED completely according to GT64260A dox - NTL */
 176        p[0] = 0x00010001;      /* 0 */
 177        p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; /* 4 */
 178        p[2] = 0;               /* 8 */
 179        p[3] = (unsigned int) &p[4];    /* c */
 180
 181#if 0
 182        p[9] = DESC_FIRST | DESC_LAST;
 183        p[10] = (unsigned int) &p[0];
 184        p[11] = (unsigned int) &p[12];
 185#endif
 186
 187        FLUSH_DCACHE (&p[0], &p[8]);
 188
 189        GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
 190                      (unsigned int) &p[0]);
 191        GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
 192                      (unsigned int) &p[0]);
 193
 194        temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF));
 195        temp |= (TX_DEMAND | TX_STOP);
 196        GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp);
 197
 198        INVALIDATE_DCACHE (&p[1], &p[2]);
 199
 200        while (p[1] & DESC_OWNER_BIT) {
 201                udelay (100);
 202                INVALIDATE_DCACHE (&p[1], &p[2]);
 203        }
 204        return 0;
 205}
 206
 207char mpsc_getchar_sdma (void)
 208{
 209        static unsigned int done = 0;
 210        volatile char ch;
 211        unsigned int len = 0, idx = 0, temp;
 212
 213        volatile unsigned int *p;
 214
 215
 216        do {
 217                p = &rx_desc_base[rx_desc_index * 8];
 218
 219                INVALIDATE_DCACHE (&p[0], &p[1]);
 220                /* Wait for character */
 221                while (p[1] & DESC_OWNER_BIT) {
 222                        udelay (100);
 223                        INVALIDATE_DCACHE (&p[0], &p[1]);
 224                }
 225
 226                /* Handle error case */
 227                if (p[1] & (1 << 15)) {
 228                        printf ("oops, error: %08x\n", p[1]);
 229
 230                        temp = GTREGREAD (GALMPSC_CHANNELREG_2 +
 231                                          (CHANNEL * GALMPSC_REG_GAP));
 232                        temp |= (1 << 23);
 233                        GT_REG_WRITE (GALMPSC_CHANNELREG_2 +
 234                                      (CHANNEL * GALMPSC_REG_GAP), temp);
 235
 236                        /* Can't poll on abort bit, so we just wait. */
 237                        udelay (100);
 238
 239                        galsdma_enable_rx ();
 240                }
 241
 242                /* Number of bytes left in this descriptor */
 243                len = p[0] & 0xffff;
 244
 245                if (len) {
 246                        /* Where to look */
 247                        idx = 5;
 248                        if (done > 3)
 249                                idx = 4;
 250                        if (done > 7)
 251                                idx = 7;
 252                        if (done > 11)
 253                                idx = 6;
 254
 255                        INVALIDATE_DCACHE (&p[idx], &p[idx + 1]);
 256                        ch = p[idx] & 0xff;
 257                        done++;
 258                }
 259
 260                if (done < len) {
 261                        /* this descriptor has more bytes still
 262                         * shift down the char we just read, and leave the
 263                         * buffer in place for the next time around
 264                         */
 265                        p[idx] = p[idx] >> 8;
 266                        FLUSH_DCACHE (&p[idx], &p[idx + 1]);
 267                }
 268
 269                if (done == len) {
 270                        /* nothing left in this descriptor.
 271                         * go to next one
 272                         */
 273                        p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;
 274                        p[0] = 0x00100000;
 275                        FLUSH_DCACHE (&p[0], &p[1]);
 276                        /* Next descriptor */
 277                        rx_desc_index = (rx_desc_index + 1) % RX_DESC;
 278                        done = 0;
 279                }
 280        } while (len == 0);     /* galileo bug.. len might be zero */
 281
 282        return ch;
 283}
 284
 285
 286int mpsc_test_char_debug (void)
 287{
 288        if ((GTREGREAD (GALMPSC_0_INT_CAUSE) & BIT6) == 0)
 289                return 0;
 290        else {
 291                return 1;
 292        }
 293}
 294
 295
 296int mpsc_test_char_sdma (void)
 297{
 298        volatile unsigned int *p = &rx_desc_base[rx_desc_index * 8];
 299
 300        INVALIDATE_DCACHE (&p[1], &p[2]);
 301
 302        if (p[1] & DESC_OWNER_BIT)
 303                return 0;
 304        else
 305                return 1;
 306}
 307
 308int mpsc_init (int baud)
 309{
 310        /* BRG CONFIG */
 311        galbrg_set_baudrate (CHANNEL, baud);
 312        galbrg_set_clksrc (CHANNEL, 8); /* set source=Tclk */
 313        galbrg_set_CUV (CHANNEL, 0);    /* set up CountUpValue */
 314        galbrg_enable (CHANNEL);        /* Enable BRG */
 315
 316        /* Set up clock routing */
 317        galmpsc_connect (CHANNEL, GALMPSC_CONNECT);     /* connect it */
 318
 319        galmpsc_route_rx_clock (CHANNEL, CHANNEL);      /* chosse BRG0 for Rx */
 320        galmpsc_route_tx_clock (CHANNEL, CHANNEL);      /* chose BRG0 for Tx */
 321
 322        /* reset MPSC state */
 323        galmpsc_shutdown (CHANNEL);
 324
 325        /* SDMA CONFIG */
 326        galsdma_set_burstsize (CHANNEL, L1_CACHE_BYTES / 8);    /* in 64 bit words (8 bytes) */
 327        galsdma_set_txle (CHANNEL);
 328        galsdma_set_rxle (CHANNEL);
 329        galsdma_set_RC (CHANNEL, 0xf);
 330        galsdma_set_SFM (CHANNEL);
 331        galsdma_set_RFT (CHANNEL);
 332
 333        /* MPSC CONFIG */
 334        galmpsc_write_config_regs (CHANNEL, GALMPSC_UART);
 335        galmpsc_config_channel_regs (CHANNEL);
 336        galmpsc_set_char_length (CHANNEL, GALMPSC_CHAR_LENGTH_8);       /* 8 */
 337        galmpsc_set_parity (CHANNEL, GALMPSC_PARITY_NONE);      /* N */
 338        galmpsc_set_stop_bit_length (CHANNEL, GALMPSC_STOP_BITS_1);     /* 1 */
 339
 340#ifdef CONFIG_MPSC_DEBUG_PORT
 341        mpsc_debug_init ();
 342#endif
 343
 344        /* COMM_MPSC CONFIG */
 345#ifdef SOFTWARE_CACHE_MANAGEMENT
 346        galmpsc_set_snoop (CHANNEL, 0); /* disable snoop */
 347#else
 348        galmpsc_set_snoop (CHANNEL, 1); /* enable snoop */
 349#endif
 350
 351        return 0;
 352}
 353
 354
 355void mpsc_sdma_init (void)
 356{
 357/* Setup SDMA channel0 SDMA_CONFIG_REG*/
 358        GT_REG_WRITE (SDMA_CONFIG_REG (0), 0x000020ff);
 359
 360/*  Enable MPSC-Window0 for DRAM Bank0   */
 361        if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT,
 362                                   MV64360_SDMA_DRAM_CS_0_TARGET,
 363                                   0,
 364                                   memoryGetBankBaseAddress
 365                                   (CS_0_LOW_DECODE_ADDRESS),
 366                                   memoryGetBankSize (BANK0)) != true)
 367                printf ("%s: SDMA_Window0 memory setup failed !!! \n",
 368                        __FUNCTION__);
 369
 370
 371/*  Disable MPSC-Window1    */
 372        if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_1_BIT,
 373                                   MV64360_SDMA_DRAM_CS_0_TARGET,
 374                                   0,
 375                                   memoryGetBankBaseAddress
 376                                   (CS_1_LOW_DECODE_ADDRESS),
 377                                   memoryGetBankSize (BANK3)) != true)
 378                printf ("%s: SDMA_Window1 memory setup failed !!! \n",
 379                        __FUNCTION__);
 380
 381
 382/*  Disable MPSC-Window2 */
 383        if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_2_BIT,
 384                                   MV64360_SDMA_DRAM_CS_0_TARGET,
 385                                   0,
 386                                   memoryGetBankBaseAddress
 387                                   (CS_2_LOW_DECODE_ADDRESS),
 388                                   memoryGetBankSize (BANK3)) != true)
 389                printf ("%s: SDMA_Window2 memory setup failed !!! \n",
 390                        __FUNCTION__);
 391
 392
 393/*  Disable MPSC-Window3 */
 394        if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_3_BIT,
 395                                   MV64360_SDMA_DRAM_CS_0_TARGET,
 396                                   0,
 397                                   memoryGetBankBaseAddress
 398                                   (CS_3_LOW_DECODE_ADDRESS),
 399                                   memoryGetBankSize (BANK3)) != true)
 400                printf ("%s: SDMA_Window3 memory setup failed !!! \n",
 401                        __FUNCTION__);
 402
 403/*  Setup MPSC0 access mode Window0 full access */
 404        GT_SET_REG_BITS (MPSC0_ACCESS_PROTECTION_REG,
 405                         (MV64360_SDMA_WIN_ACCESS_FULL <<
 406                          (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
 407
 408/*  Setup MPSC1 access mode Window1 full access */
 409        GT_SET_REG_BITS (MPSC1_ACCESS_PROTECTION_REG,
 410                         (MV64360_SDMA_WIN_ACCESS_FULL <<
 411                          (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
 412
 413/* Setup MPSC internal address space base address       */
 414        GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CONFIG_SYS_GT_REGS);
 415
 416/* no high address remap*/
 417        GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00);
 418        GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG1, 0x00);
 419
 420/* clear interrupt cause register for MPSC (fault register)*/
 421        GT_REG_WRITE (CUNIT_INTERRUPT_CAUSE_REG, 0x00);
 422}
 423
 424
 425void mpsc_init2 (void)
 426{
 427        int i;
 428
 429#ifndef CONFIG_MPSC_DEBUG_PORT
 430        mpsc_putchar = mpsc_putchar_sdma;
 431        mpsc_getchar = mpsc_getchar_sdma;
 432        mpsc_test_char = mpsc_test_char_sdma;
 433#endif
 434        /* RX descriptors */
 435        rx_desc_base = (unsigned int *) malloc (((RX_DESC + 1) * 8) *
 436                                                sizeof (unsigned int));
 437
 438        /* align descriptors */
 439        rx_desc_base = (unsigned int *)
 440                (((unsigned int) rx_desc_base + 32) & 0xFFFFFFF0);
 441
 442        rx_desc_index = 0;
 443
 444        memset ((void *) rx_desc_base, 0,
 445                (RX_DESC * 8) * sizeof (unsigned int));
 446
 447        for (i = 0; i < RX_DESC; i++) {
 448                rx_desc_base[i * 8 + 3] = (unsigned int) &rx_desc_base[i * 8 + 4];      /* Buffer */
 449                rx_desc_base[i * 8 + 2] = (unsigned int) &rx_desc_base[(i + 1) * 8];    /* Next descriptor */
 450                rx_desc_base[i * 8 + 1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;      /* Command & control */
 451                rx_desc_base[i * 8] = 0x00100000;
 452        }
 453        rx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &rx_desc_base[0];
 454
 455        FLUSH_DCACHE (&rx_desc_base[0], &rx_desc_base[RX_DESC * 8]);
 456        GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
 457                      (unsigned int) &rx_desc_base[0]);
 458
 459        /* TX descriptors */
 460        tx_desc_base = (unsigned int *) malloc (((TX_DESC + 1) * 8) *
 461                                                sizeof (unsigned int));
 462
 463        /* align descriptors */
 464        tx_desc_base = (unsigned int *)
 465                (((unsigned int) tx_desc_base + 32) & 0xFFFFFFF0);
 466
 467        tx_desc_index = -1;
 468
 469        memset ((void *) tx_desc_base, 0,
 470                (TX_DESC * 8) * sizeof (unsigned int));
 471
 472        for (i = 0; i < TX_DESC; i++) {
 473                tx_desc_base[i * 8 + 5] = (unsigned int) 0x23232323;
 474                tx_desc_base[i * 8 + 4] = (unsigned int) 0x23232323;
 475                tx_desc_base[i * 8 + 3] =
 476                        (unsigned int) &tx_desc_base[i * 8 + 4];
 477                tx_desc_base[i * 8 + 2] =
 478                        (unsigned int) &tx_desc_base[(i + 1) * 8];
 479                tx_desc_base[i * 8 + 1] =
 480                        DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;
 481
 482                /* set sbytecnt and shadow byte cnt to 1 */
 483                tx_desc_base[i * 8] = 0x00010001;
 484        }
 485        tx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &tx_desc_base[0];
 486
 487        FLUSH_DCACHE (&tx_desc_base[0], &tx_desc_base[TX_DESC * 8]);
 488
 489        udelay (100);
 490
 491        galsdma_enable_rx ();
 492
 493        return;
 494}
 495
 496int galbrg_set_baudrate (int channel, int rate)
 497{
 498        int clock;
 499
 500        galbrg_disable (channel);       /*ok */
 501
 502#ifdef ZUMA_NTL
 503        /* from tclk */
 504        clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
 505#else
 506        clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
 507#endif
 508
 509        galbrg_set_CDV (channel, clock);        /* set timer Reg. for BRG */
 510
 511        galbrg_enable (channel);
 512
 513        gd->baudrate = rate;
 514
 515        return 0;
 516}
 517
 518/* ------------------------------------------------------------------ */
 519
 520/* Below are all the private functions that no one else needs */
 521
 522static int galbrg_set_CDV (int channel, int value)
 523{
 524        unsigned int temp;
 525
 526        temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
 527        temp &= 0xFFFF0000;
 528        temp |= (value & 0x0000FFFF);
 529        GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
 530
 531        return 0;
 532}
 533
 534static int galbrg_enable (int channel)
 535{
 536        unsigned int temp;
 537
 538        temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
 539        temp |= 0x00010000;
 540        GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
 541
 542        return 0;
 543}
 544
 545static int galbrg_disable (int channel)
 546{
 547        unsigned int temp;
 548
 549        temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
 550        temp &= 0xFFFEFFFF;
 551        GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
 552
 553        return 0;
 554}
 555
 556static int galbrg_set_clksrc (int channel, int value)
 557{
 558        unsigned int temp;
 559
 560        temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
 561        temp &= 0xFFC3FFFF;     /* Bit 18 - 21 (MV 64260 18-22) */
 562        temp |= (value << 18);
 563        GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
 564        return 0;
 565}
 566
 567static int galbrg_set_CUV (int channel, int value)
 568{
 569        /* set CountUpValue */
 570        GT_REG_WRITE (GALBRG_0_BTREG + (channel * GALBRG_REG_GAP), value);
 571
 572        return 0;
 573}
 574
 575#if 0
 576static int galbrg_reset (int channel)
 577{
 578        unsigned int temp;
 579
 580        temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
 581        temp |= 0x20000;
 582        GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
 583
 584        return 0;
 585}
 586#endif
 587
 588static int galsdma_set_RFT (int channel)
 589{
 590        unsigned int temp;
 591
 592        temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
 593        temp |= 0x00000001;
 594        GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
 595                      temp);
 596
 597        return 0;
 598}
 599
 600static int galsdma_set_SFM (int channel)
 601{
 602        unsigned int temp;
 603
 604        temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
 605        temp |= 0x00000002;
 606        GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
 607                      temp);
 608
 609        return 0;
 610}
 611
 612static int galsdma_set_rxle (int channel)
 613{
 614        unsigned int temp;
 615
 616        temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
 617        temp |= 0x00000040;
 618        GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
 619                      temp);
 620
 621        return 0;
 622}
 623
 624static int galsdma_set_txle (int channel)
 625{
 626        unsigned int temp;
 627
 628        temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
 629        temp |= 0x00000080;
 630        GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
 631                      temp);
 632
 633        return 0;
 634}
 635
 636static int galsdma_set_RC (int channel, unsigned int value)
 637{
 638        unsigned int temp;
 639
 640        temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
 641        temp &= ~0x0000003c;
 642        temp |= (value << 2);
 643        GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
 644                      temp);
 645
 646        return 0;
 647}
 648
 649static int galsdma_set_burstsize (int channel, unsigned int value)
 650{
 651        unsigned int temp;
 652
 653        temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
 654        temp &= 0xFFFFCFFF;
 655        switch (value) {
 656        case 8:
 657                GT_REG_WRITE (GALSDMA_0_CONF_REG +
 658                              (channel * GALSDMA_REG_DIFF),
 659                              (temp | (0x3 << 12)));
 660                break;
 661
 662        case 4:
 663                GT_REG_WRITE (GALSDMA_0_CONF_REG +
 664                              (channel * GALSDMA_REG_DIFF),
 665                              (temp | (0x2 << 12)));
 666                break;
 667
 668        case 2:
 669                GT_REG_WRITE (GALSDMA_0_CONF_REG +
 670                              (channel * GALSDMA_REG_DIFF),
 671                              (temp | (0x1 << 12)));
 672                break;
 673
 674        case 1:
 675                GT_REG_WRITE (GALSDMA_0_CONF_REG +
 676                              (channel * GALSDMA_REG_DIFF),
 677                              (temp | (0x0 << 12)));
 678                break;
 679
 680        default:
 681                return -1;
 682                break;
 683        }
 684
 685        return 0;
 686}
 687
 688static int galmpsc_connect (int channel, int connect)
 689{
 690        unsigned int temp;
 691
 692        temp = GTREGREAD (GALMPSC_ROUTING_REGISTER);
 693
 694        if ((channel == 0) && connect)
 695                temp &= ~0x00000007;
 696        else if ((channel == 1) && connect)
 697                temp &= ~(0x00000007 << 6);
 698        else if ((channel == 0) && !connect)
 699                temp |= 0x00000007;
 700        else
 701                temp |= (0x00000007 << 6);
 702
 703        /* Just in case... */
 704        temp &= 0x3fffffff;
 705
 706        GT_REG_WRITE (GALMPSC_ROUTING_REGISTER, temp);
 707
 708        return 0;
 709}
 710
 711static int galmpsc_route_rx_clock (int channel, int brg)
 712{
 713        unsigned int temp;
 714
 715        temp = GTREGREAD (GALMPSC_RxC_ROUTE);
 716
 717        if (channel == 0) {
 718                temp &= ~0x0000000F;
 719                temp |= brg;
 720        } else {
 721                temp &= ~0x00000F00;
 722                temp |= (brg << 8);
 723        }
 724
 725        GT_REG_WRITE (GALMPSC_RxC_ROUTE, temp);
 726
 727        return 0;
 728}
 729
 730static int galmpsc_route_tx_clock (int channel, int brg)
 731{
 732        unsigned int temp;
 733
 734        temp = GTREGREAD (GALMPSC_TxC_ROUTE);
 735
 736        if (channel == 0) {
 737                temp &= ~0x0000000F;
 738                temp |= brg;
 739        } else {
 740                temp &= ~0x00000F00;
 741                temp |= (brg << 8);
 742        }
 743
 744        GT_REG_WRITE (GALMPSC_TxC_ROUTE, temp);
 745
 746        return 0;
 747}
 748
 749static int galmpsc_write_config_regs (int mpsc, int mode)
 750{
 751        if (mode == GALMPSC_UART) {
 752                /* Main config reg Low (Null modem, Enable Tx/Rx, UART mode) */
 753                GT_REG_WRITE (GALMPSC_MCONF_LOW + (mpsc * GALMPSC_REG_GAP),
 754                              0x000004c4);
 755
 756                /* Main config reg High (32x Rx/Tx clock mode, width=8bits */
 757                GT_REG_WRITE (GALMPSC_MCONF_HIGH + (mpsc * GALMPSC_REG_GAP),
 758                              0x024003f8);
 759                /*        22 2222 1111 */
 760                /*        54 3210 9876 */
 761                /* 0000 0010 0000 0000 */
 762                /*       1 */
 763                /*       098 7654 3210 */
 764                /* 0000 0011 1111 1000 */
 765        } else
 766                return -1;
 767
 768        return 0;
 769}
 770
 771static int galmpsc_config_channel_regs (int mpsc)
 772{
 773        GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), 0);
 774        GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), 0);
 775        GT_REG_WRITE (GALMPSC_CHANNELREG_3 + (mpsc * GALMPSC_REG_GAP), 1);
 776        GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (mpsc * GALMPSC_REG_GAP), 0);
 777        GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (mpsc * GALMPSC_REG_GAP), 0);
 778        GT_REG_WRITE (GALMPSC_CHANNELREG_6 + (mpsc * GALMPSC_REG_GAP), 0);
 779        GT_REG_WRITE (GALMPSC_CHANNELREG_7 + (mpsc * GALMPSC_REG_GAP), 0);
 780        GT_REG_WRITE (GALMPSC_CHANNELREG_8 + (mpsc * GALMPSC_REG_GAP), 0);
 781        GT_REG_WRITE (GALMPSC_CHANNELREG_9 + (mpsc * GALMPSC_REG_GAP), 0);
 782        GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (mpsc * GALMPSC_REG_GAP), 0);
 783
 784        galmpsc_set_brkcnt (mpsc, 0x3);
 785        galmpsc_set_tcschar (mpsc, 0xab);
 786
 787        return 0;
 788}
 789
 790static int galmpsc_set_brkcnt (int mpsc, int value)
 791{
 792        unsigned int temp;
 793
 794        temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP));
 795        temp &= 0x0000FFFF;
 796        temp |= (value << 16);
 797        GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp);
 798
 799        return 0;
 800}
 801
 802static int galmpsc_set_tcschar (int mpsc, int value)
 803{
 804        unsigned int temp;
 805
 806        temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP));
 807        temp &= 0xFFFF0000;
 808        temp |= value;
 809        GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp);
 810
 811        return 0;
 812}
 813
 814static int galmpsc_set_char_length (int mpsc, int value)
 815{
 816        unsigned int temp;
 817
 818        temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP));
 819        temp &= 0xFFFFCFFF;
 820        temp |= (value << 12);
 821        GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp);
 822
 823        return 0;
 824}
 825
 826static int galmpsc_set_stop_bit_length (int mpsc, int value)
 827{
 828        unsigned int temp;
 829
 830        temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP));
 831        temp &= 0xFFFFBFFF;
 832        temp |= (value << 14);
 833        GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp);
 834
 835        return 0;
 836}
 837
 838static int galmpsc_set_parity (int mpsc, int value)
 839{
 840        unsigned int temp;
 841
 842        temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
 843        if (value != -1) {
 844                temp &= 0xFFF3FFF3;
 845                temp |= ((value << 18) | (value << 2));
 846                temp |= ((value << 17) | (value << 1));
 847        } else {
 848                temp &= 0xFFF1FFF1;
 849        }
 850
 851        GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
 852
 853        return 0;
 854}
 855
 856static int galmpsc_enter_hunt (int mpsc)
 857{
 858        int temp;
 859
 860        temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
 861        temp |= 0x80000000;
 862        GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
 863
 864        while (GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)) &
 865               MPSC_ENTER_HUNT) {
 866                udelay (1);
 867        }
 868        return 0;
 869}
 870
 871
 872static int galmpsc_shutdown (int mpsc)
 873{
 874        unsigned int temp;
 875
 876        /* cause RX abort (clears RX) */
 877        temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
 878        temp |= MPSC_RX_ABORT | MPSC_TX_ABORT;
 879        temp &= ~MPSC_ENTER_HUNT;
 880        GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
 881
 882        GT_REG_WRITE (GALSDMA_0_COM_REG, 0);
 883        GT_REG_WRITE (GALSDMA_0_COM_REG, SDMA_TX_ABORT | SDMA_RX_ABORT);
 884
 885        /* shut down the MPSC */
 886        GT_REG_WRITE (GALMPSC_MCONF_LOW, 0);
 887        GT_REG_WRITE (GALMPSC_MCONF_HIGH, 0);
 888        GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), 0);
 889
 890        udelay (100);
 891
 892        /* shut down the sdma engines. */
 893        /* reset config to default */
 894        GT_REG_WRITE (GALSDMA_0_CONF_REG, 0x000000fc);
 895
 896        udelay (100);
 897
 898        /* clear the SDMA current and first TX and RX pointers */
 899        GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR, 0);
 900        GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR, 0);
 901        GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR, 0);
 902
 903        udelay (100);
 904
 905        return 0;
 906}
 907
 908static void galsdma_enable_rx (void)
 909{
 910        int temp;
 911
 912        /* Enable RX processing */
 913        temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF));
 914        temp |= RX_ENABLE;
 915        GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp);
 916
 917        galmpsc_enter_hunt (CHANNEL);
 918}
 919
 920static int galmpsc_set_snoop (int mpsc, int value)
 921{
 922        int reg =
 923                mpsc ? MPSC_1_ADDRESS_CONTROL_LOW :
 924                MPSC_0_ADDRESS_CONTROL_LOW;
 925        int temp = GTREGREAD (reg);
 926
 927        if (value)
 928                temp |= (1 << 6) | (1 << 14) | (1 << 22) | (1 << 30);
 929        else
 930                temp &= ~((1 << 6) | (1 << 14) | (1 << 22) | (1 << 30));
 931        GT_REG_WRITE (reg, temp);
 932        return 0;
 933}
 934
 935/*******************************************************************************
 936* galsdma_set_mem_space - Set MV64360 IDMA memory decoding map.
 937*
 938* DESCRIPTION:
 939*       the MV64360 SDMA has its own address decoding map that is de-coupled
 940*       from the CPU interface address decoding windows. The SDMA channels
 941*       share four address windows. Each region can be individually configured
 942*       by this function by associating it to a target interface and setting
 943*       base and size values.
 944*
 945*      NOTE!!!
 946*       The size must be in 64Kbyte granularity.
 947*       The base address must be aligned to the size.
 948*       The size must be a series of 1s followed by a series of zeros
 949*
 950* OUTPUT:
 951*       None.
 952*
 953* RETURN:
 954*       true for success, false otherwise.
 955*
 956*******************************************************************************/
 957
 958static int galsdma_set_mem_space (unsigned int memSpace,
 959                                  unsigned int memSpaceTarget,
 960                                  unsigned int memSpaceAttr,
 961                                  unsigned int baseAddress, unsigned int size)
 962{
 963        unsigned int temp;
 964
 965        if (size == 0) {
 966                GT_RESET_REG_BITS (MV64360_CUNIT_BASE_ADDR_ENABLE_REG,
 967                                   1 << memSpace);
 968                return true;
 969        }
 970
 971        /* The base address must be aligned to the size.  */
 972        if (baseAddress % size != 0) {
 973                return false;
 974        }
 975        if (size < 0x10000) {
 976                return false;
 977        }
 978
 979        /* Align size and base to 64K */
 980        baseAddress &= 0xffff0000;
 981        size &= 0xffff0000;
 982        temp = size >> 16;
 983
 984        /* Checking that the size is a sequence of '1' followed by a
 985           sequence of '0' starting from LSB to MSB. */
 986        while ((temp > 0) && (temp & 0x1)) {
 987                temp = temp >> 1;
 988        }
 989
 990        if (temp != 0) {
 991                GT_REG_WRITE (MV64360_CUNIT_BASE_ADDR_REG0 + memSpace * 8,
 992                              (baseAddress | memSpaceTarget | memSpaceAttr));
 993                GT_REG_WRITE ((MV64360_CUNIT_SIZE0 + memSpace * 8),
 994                              (size - 1) & 0xffff0000);
 995                GT_RESET_REG_BITS (MV64360_CUNIT_BASE_ADDR_ENABLE_REG,
 996                                   1 << memSpace);
 997        } else {
 998                /* An invalid size was specified */
 999                return false;
1000        }

1001        return true;
1002}
1003