LXR uboot/board/evb64260/misc.S

   1#include <config.h>
   2#include <74xx_7xx.h>
   3#include <version.h>
   4
   5#include <ppc_asm.tmpl>
   6#include <ppc_defs.h>
   7
   8#include <asm/cache.h>
   9#include <asm/mmu.h>
  10
  11#include <galileo/gt64260R.h>
  12
  13#ifdef CONFIG_ECC
  14        /* Galileo specific asm code for initializing ECC */
  15        .globl board_relocate_rom
  16board_relocate_rom:
  17        mflr    r7
  18        /* update the location of the GT registers */
  19        lis     r11, CONFIG_SYS_GT_REGS@h
  20        /* if we're using ECC, we must use the DMA engine to copy ourselves */
  21        bl      start_idma_transfer_0
  22        bl      wait_for_idma_0
  23        bl      stop_idma_engine_0
  24
  25        mtlr    r7
  26        blr
  27
  28        .globl board_init_ecc
  29board_init_ecc:
  30        mflr    r7
  31        /* NOTE: r10 still contains the location we've been relocated to
  32         * which happens to be TOP_OF_RAM - CONFIG_SYS_MONITOR_LEN */
  33
  34        /* now that we're running from ram, init the rest of main memory
  35         * for ECC use */
  36        lis     r8, CONFIG_SYS_MONITOR_LEN@h
  37        ori     r8, r8, CONFIG_SYS_MONITOR_LEN@l
  38
  39        divw    r3, r10, r8
  40
  41        /* set up the counter, and init the starting address */
  42        mtctr   r3
  43        li      r12, 0
  44
  45        /* bytes per transfer */
  46        mr      r5, r8
  47about_to_init_ecc:
  481:      mr      r3, r12
  49        mr      r4, r12
  50        bl      start_idma_transfer_0
  51        bl      wait_for_idma_0
  52        bl      stop_idma_engine_0
  53        add     r12, r12, r8
  54        bdnz    1b
  55
  56        mtlr    r7
  57        blr
  58
  59        /* r3:  dest addr
  60         * r4:  source addr
  61         * r5:  byte count
  62         * r11: gt regbase
  63         * trashes:      r6, r5
  64         */
  65start_idma_transfer_0:
  66        /* set the byte count, including the OWN bit */
  67        mr      r6, r11
  68        ori     r6, r6, CHANNEL0_DMA_BYTE_COUNT
  69        stwbrx  r5, 0, (r6)
  70
  71        /* set the source address */
  72        mr      r6, r11
  73        ori     r6, r6, CHANNEL0_DMA_SOURCE_ADDRESS
  74        stwbrx  r4, 0, (r6)
  75
  76        /* set the dest address */
  77        mr      r6, r11
  78        ori     r6, r6, CHANNEL0_DMA_DESTINATION_ADDRESS
  79        stwbrx  r3, 0, (r6)
  80
  81        /* set the next record pointer */
  82        li      r5, 0
  83        mr      r6, r11
  84        ori     r6, r6, CHANNEL0NEXT_RECORD_POINTER
  85        stwbrx  r5, 0, (r6)
  86
  87        /* set the low control register */
  88        /* bit 9 is NON chained mode, bit 31 is new style descriptors.
  89           bit 12 is channel enable */
  90        ori     r5, r5, (1 << 12) | (1 << 12) | (1 << 11)
  91        /* 15 shifted by 16 (oris) == bit 31 */
  92        oris    r5, r5, (1 << 15)
  93        mr      r6, r11
  94        ori     r6, r6, CHANNEL0CONTROL
  95        stwbrx  r5, 0, (r6)
  96
  97        blr
  98
  99        /* this waits for the bytecount to return to zero, indicating
 100         * that the trasfer is complete */
 101wait_for_idma_0:
 102        mr      r5, r11
 103        lis     r6, 0xff
 104        ori     r6, r6, 0xffff
 105        ori     r5, r5, CHANNEL0_DMA_BYTE_COUNT
 1061:      lwbrx   r4, 0, (r5)
 107        and.    r4, r4, r6
 108        bne     1b
 109
 110        blr
 111
 112        /* this turns off channel 0 of the idma engine */
 113stop_idma_engine_0:
 114        /* shut off the DMA engine */
 115        li      r5, 0
 116        mr      r6, r11
 117        ori     r6, r6, CHANNEL0CONTROL
 118        stwbrx  r5, 0, (r6)
 119
 120        blr
 121#endif
 122
 123#ifdef CONFIG_SYS_BOARD_ASM_INIT
 124        /* NOTE: trashes r3-r7 */
 125        .globl board_asm_init
 126board_asm_init:
 127        /* just move the GT registers to where they belong */
 128        lis     r3, CONFIG_SYS_DFL_GT_REGS@h
 129        ori     r3, r3, CONFIG_SYS_DFL_GT_REGS@l
 130        lis     r4, CONFIG_SYS_GT_REGS@h
 131        ori     r4, r4, CONFIG_SYS_GT_REGS@l
 132        li      r5, INTERNAL_SPACE_DECODE
 133
 134        /* test to see if we've already moved */
 135        lwbrx   r6, r5, r4
 136        andi.   r6, r6, 0xffff
 137        rlwinm  r7, r4, 12, 16, 31
 138        cmp     cr0, r7, r6
 139        beqlr
 140
 141        /* nope, have to move the registers */
 142        lwbrx   r6, r5, r3
 143        andis.  r6, r6, 0xffff
 144        or      r6, r6, r7
 145        stwbrx  r6, r5, r3
 146
 147        /* now, poll for the change */
 1481:      lwbrx   r7, r5, r4
 149        cmp     cr0, r7, r6
 150        bne     1b
 151
 152        /* done! */
 153        blr
 154#endif
 155
 156/* For use of the debug LEDs */
 157        .global led_on0
 158led_on0:
 159        xor     r18, r18, r18
 160        lis     r18, 0x1c80
 161        ori     r18, r18, 0x8000
 162        stw     r18, 0x0(r18)
 163        sync
 164        blr
 165
 166        .global led_on1
 167led_on1:
 168        xor     r18, r18, r18
 169        lis     r18, 0x1c80
 170        ori     r18, r18, 0xc000
 171        stw     r18, 0x0(r18)
 172        sync
 173        blr
 174
 175        .global led_on2
 176led_on2:
 177        xor     r18, r18, r18
 178        lis     r18, 0x1c81
 179        ori     r18, r18, 0x0000
 180        stw     r18, 0x0(r18)
 181        sync
 182        blr
 183