LXR uboot/board/evb64260/mpsc.h

   1/*
   2 * (C) Copyright 2001
   3 * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 */
   7
   8/*
   9 * mpsc.h - header file for MPSC in uart mode (console driver)
  10 */
  11
  12#ifndef __MPSC_H__
  13#define __MPSC_H__
  14
  15/* include actual Galileo defines */
  16#include <galileo/gt64260R.h>
  17
  18/* driver related defines */
  19
  20int mpsc_init(int baud);
  21void mpsc_init2(void);
  22char mpsc_getchar(void);
  23int mpsc_test_char(void);
  24int galbrg_set_baudrate(int channel, int rate);
  25
  26int mpsc_putchar_early(char ch);
  27extern int (*mpsc_putchar)(char ch);
  28
  29#define CHANNEL CONFIG_MPSC_PORT
  30
  31#define TX_DESC     5
  32#define RX_DESC     20
  33
  34#define DESC_FIRST  0x00010000
  35#define DESC_LAST   0x00020000
  36#define DESC_OWNER  0x80000000
  37
  38#define TX_DEMAND   0x00800000
  39#define TX_STOP     0x00010000
  40#define RX_ENABLE   0x00000080
  41
  42#define SDMA_RX_ABORT             (1 << 15)
  43#define SDMA_TX_ABORT             (1 << 31)
  44#define MPSC_TX_ABORT             (1 << 7)
  45#define MPSC_RX_ABORT             (1 << 23)
  46#define MPSC_ENTER_HUNT           (1 << 31)
  47
  48/* MPSC defines */
  49
  50#define GALMPSC_CONNECT            0x1
  51#define GALMPSC_DISCONNECT         0x0
  52
  53#define GALMPSC_UART               0x1
  54
  55#define GALMPSC_STOP_BITS_1        0x0
  56#define GALMPSC_STOP_BITS_2        0x1
  57#define GALMPSC_CHAR_LENGTH_8      0x3
  58#define GALMPSC_CHAR_LENGTH_7      0x2
  59
  60#define GALMPSC_PARITY_ODD         0x0
  61#define GALMPSC_PARITY_EVEN        0x2
  62#define GALMPSC_PARITY_MARK        0x3
  63#define GALMPSC_PARITY_SPACE       0x1
  64#define GALMPSC_PARITY_NONE        -1
  65
  66#define GALMPSC_SERIAL_MULTIPLEX   SERIAL_PORT_MULTIPLEX           /* 0xf010 */
  67#define GALMPSC_ROUTING_REGISTER   MAIN_ROUTING_REGISTER           /* 0xb400 */
  68#define GALMPSC_RxC_ROUTE          RECEIVE_CLOCK_ROUTING_REGISTER  /* 0xb404 */
  69#define GALMPSC_TxC_ROUTE          TRANSMIT_CLOCK_ROUTING_REGISTER /* 0xb408 */
  70#define GALMPSC_MCONF_LOW          MPSC0_MAIN_CONFIGURATION_LOW    /* 0x8000 */
  71#define GALMPSC_MCONF_HIGH         MPSC0_MAIN_CONFIGURATION_HIGH   /* 0x8004 */
  72#define GALMPSC_PROTOCONF_REG      MPSC0_PROTOCOL_CONFIGURATION    /* 0x8008 */
  73
  74#define GALMPSC_REG_GAP            0x1000
  75
  76#define GALMPSC_MCONF_CHREG_BASE   CHANNEL0_REGISTER1  /* 0x800c */
  77#define GALMPSC_CHANNELREG_1       CHANNEL0_REGISTER1  /* 0x800c */
  78#define GALMPSC_CHANNELREG_2       CHANNEL0_REGISTER2  /* 0x8010 */
  79#define GALMPSC_CHANNELREG_3       CHANNEL0_REGISTER3  /* 0x8014 */
  80#define GALMPSC_CHANNELREG_4       CHANNEL0_REGISTER4  /* 0x8018 */
  81#define GALMPSC_CHANNELREG_5       CHANNEL0_REGISTER5  /* 0x801c */
  82#define GALMPSC_CHANNELREG_6       CHANNEL0_REGISTER6  /* 0x8020 */
  83#define GALMPSC_CHANNELREG_7       CHANNEL0_REGISTER7  /* 0x8024 */
  84#define GALMPSC_CHANNELREG_8       CHANNEL0_REGISTER8  /* 0x8028 */
  85#define GALMPSC_CHANNELREG_9       CHANNEL0_REGISTER9  /* 0x802c */
  86#define GALMPSC_CHANNELREG_10      CHANNEL0_REGISTER10 /* 0x8030 */
  87#define GALMPSC_CHANNELREG_11      CHANNEL0_REGISTER11 /* 0x8034 */
  88
  89#define GALSDMA_COMMAND_FIRST     (1 << 16)
  90#define GALSDMA_COMMAND_LAST      (1 << 17)
  91#define GALSDMA_COMMAND_ENABLEINT (1 << 23)
  92#define GALSDMA_COMMAND_AUTO      (1 << 30)
  93#define GALSDMA_COMMAND_OWNER     (1 << 31)
  94
  95#define GALSDMA_RX                 0
  96#define GALSDMA_TX                 1
  97
  98/* CHANNEL2 should be CHANNEL1, according to documentation,
  99 * but to work with the current GTREGS file...
 100 */
 101#define GALSDMA_0_CONF_REG         CHANNEL0_CONFIGURATION_REGISTER   /* 0x4000 */
 102#define GALSDMA_1_CONF_REG         CHANNEL2_CONFIGURATION_REGISTER   /* 0x6000 */
 103#define GALSDMA_0_COM_REG          CHANNEL0_COMMAND_REGISTER         /* 0x4008 */
 104#define GALSDMA_1_COM_REG          CHANNEL2_COMMAND_REGISTER         /* 0x6008 */
 105#define GALSDMA_0_CUR_RX_PTR       CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER  /* 0x4810 */
 106#define GALSDMA_0_CUR_TX_PTR       CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER  /* 0x4c10 */
 107#define GALSDMA_0_FIR_TX_PTR       CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER    /* 0x4c14 */
 108#define GALSDMA_1_CUR_RX_PTR       CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER  /* 0x6810 */
 109#define GALSDMA_1_CUR_TX_PTR       CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER  /* 0x6c10 */
 110#define GALSDMA_1_FIR_TX_PTR       CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER    /* 0x6c14 */
 111#define GALSDMA_REG_DIFF           0x2000
 112
 113/* WRONG in gt64260R.h */
 114#define GALSDMA_INT_CAUSE          0xb800   /* SDMA_CAUSE */
 115#define GALSDMA_INT_MASK           0xb880   /* SDMA_MASK  */
 116
 117#define GALSDMA_MODE_UART          0
 118#define GALSDMA_MODE_BISYNC        1
 119#define GALSDMA_MODE_HDLC          2
 120#define GALSDMA_MODE_TRANSPARENT   3
 121
 122#define GALBRG_0_CONFREG           BRG0_CONFIGURATION_REGISTER  /*  0xb200  */
 123#define GALBRG_REG_GAP             0x0008
 124#define GALBRG_0_BTREG             BRG0_BAUDE_TUNING_REGISTER   /*  0xb204  */
 125
 126#endif /* __MPSC_H__ */
 127