LXR uboot/board/freescale/mpc7448hpc2/tsi108

   1/*****************************************************************************
   2 * (C) Copyright 2003;  Tundra Semiconductor Corp.
   3 *
   4 * SPDX-License-Identifier:     GPL-2.0+
   5 *****************************************************************************/
   6
   7/*----------------------------------------------------------------------------
   8 * FILENAME: tsi108_init.c
   9 *
  10 * Originator: Alex Bounine
  11 *
  12 * DESCRIPTION:
  13 * Initialization code for the Tundra Tsi108 bridge chip
  14 *---------------------------------------------------------------------------*/
  15
  16#include <common.h>
  17#include <74xx_7xx.h>
  18#include <config.h>
  19#include <version.h>
  20#include <asm/processor.h>
  21#include <tsi108.h>
  22
  23DECLARE_GLOBAL_DATA_PTR;
  24
  25extern void mpicInit (int verbose);
  26
  27/*
  28 * Configuration Options
  29 */
  30
  31typedef struct {
  32        ulong upper;
  33        ulong lower;
  34} PB2OCN_LUT_ENTRY;
  35
  36PB2OCN_LUT_ENTRY pb2ocn_lut1[32] = {
  37        /* 0 - 7 */
  38        {0x00000000, 0x00000201}, /* PBA=0xE000_0000 -> PCI/X (Byte-Swap) */
  39        {0x00000000, 0x00000201}, /* PBA=0xE100_0000 -> PCI/X (Byte-Swap) */
  40        {0x00000000, 0x00000201}, /* PBA=0xE200_0000 -> PCI/X (Byte-Swap) */
  41        {0x00000000, 0x00000201}, /* PBA=0xE300_0000 -> PCI/X (Byte-Swap) */
  42        {0x00000000, 0x00000201}, /* PBA=0xE400_0000 -> PCI/X (Byte-Swap) */
  43        {0x00000000, 0x00000201}, /* PBA=0xE500_0000 -> PCI/X (Byte-Swap) */
  44        {0x00000000, 0x00000201}, /* PBA=0xE600_0000 -> PCI/X (Byte-Swap) */
  45        {0x00000000, 0x00000201}, /* PBA=0xE700_0000 -> PCI/X (Byte-Swap) */
  46
  47        /* 8 - 15 */
  48        {0x00000000, 0x00000201}, /* PBA=0xE800_0000 -> PCI/X (Byte-Swap) */
  49        {0x00000000, 0x00000201}, /* PBA=0xE900_0000 -> PCI/X (Byte-Swap) */
  50        {0x00000000, 0x00000201}, /* PBA=0xEA00_0000 -> PCI/X (Byte-Swap) */
  51        {0x00000000, 0x00000201}, /* PBA=0xEB00_0000 -> PCI/X (Byte-Swap) */
  52        {0x00000000, 0x00000201}, /* PBA=0xEC00_0000 -> PCI/X (Byte-Swap) */
  53        {0x00000000, 0x00000201}, /* PBA=0xED00_0000 -> PCI/X (Byte-Swap) */
  54        {0x00000000, 0x00000201}, /* PBA=0xEE00_0000 -> PCI/X (Byte-Swap) */
  55        {0x00000000, 0x00000201}, /* PBA=0xEF00_0000 -> PCI/X (Byte-Swap) */
  56
  57        /* 16 - 23 */
  58        {0x00000000, 0x00000201}, /* PBA=0xF000_0000 -> PCI/X (Byte-Swap) */
  59        {0x00000000, 0x00000201}, /* PBA=0xF100_0000 -> PCI/X (Byte-Swap) */
  60        {0x00000000, 0x00000201}, /* PBA=0xF200_0000 -> PCI/X (Byte-Swap) */
  61        {0x00000000, 0x00000201}, /* PBA=0xF300_0000 -> PCI/X (Byte-Swap) */
  62        {0x00000000, 0x00000201}, /* PBA=0xF400_0000 -> PCI/X (Byte-Swap) */
  63        {0x00000000, 0x00000201}, /* PBA=0xF500_0000 -> PCI/X (Byte-Swap) */
  64        {0x00000000, 0x00000201}, /* PBA=0xF600_0000 -> PCI/X (Byte-Swap) */
  65        {0x00000000, 0x00000201}, /* PBA=0xF700_0000 -> PCI/X (Byte-Swap) */
  66        /* 24 - 31 */
  67        {0x00000000, 0x00000201}, /* PBA=0xF800_0000 -> PCI/X (Byte-Swap) */
  68        {0x00000000, 0x00000201}, /* PBA=0xF900_0000 -> PCI/X (Byte-Swap) */
  69        {0x00000000, 0x00000241}, /* PBA=0xFA00_0000 -> PCI/X  PCI I/O (Byte-Swap + Translate) */
  70        {0x00000000, 0x00000201}, /* PBA=0xFB00_0000 -> PCI/X  PCI Config (Byte-Swap) */
  71
  72        {0x00000000, 0x02000240}, /* PBA=0xFC00_0000 -> HLP */
  73        {0x00000000, 0x01000240}, /* PBA=0xFD00_0000 -> HLP */
  74        {0x00000000, 0x03000240}, /* PBA=0xFE00_0000 -> HLP */
  75        {0x00000000, 0x00000240}  /* PBA=0xFF00_0000 -> HLP : (Translation Enabled + Byte-Swap)*/
  76};
  77
  78#ifdef CONFIG_SYS_CLK_SPREAD
  79typedef struct {
  80        ulong ctrl0;
  81        ulong ctrl1;
  82} PLL_CTRL_SET;
  83
  84/*
  85 * Clock Generator SPLL0 initialization values
  86 * PLL0 configuration table for various PB_CLKO freq.
  87 * Uses pre-calculated values for Fs = 30 kHz, D = 0.5%
  88 * Fout depends on required PB_CLKO. Based on Fref = 33 MHz
  89 */
  90
  91static PLL_CTRL_SET pll0_config[8] = {
  92        {0x00000000, 0x00000000},       /* 0: bypass */
  93        {0x00000000, 0x00000000},       /* 1: reserved */
  94        {0x00430044, 0x00000043},       /* 2: CG_PB_CLKO = 183 MHz */
  95        {0x005c0044, 0x00000039},       /* 3: CG_PB_CLKO = 100 MHz */
  96        {0x005c0044, 0x00000039},       /* 4: CG_PB_CLKO = 133 MHz */
  97        {0x004a0044, 0x00000040},       /* 5: CG_PB_CLKO = 167 MHz */
  98        {0x005c0044, 0x00000039},       /* 6: CG_PB_CLKO = 200 MHz */
  99        {0x004f0044, 0x0000003e}        /* 7: CG_PB_CLKO = 233 MHz */
 100};
 101#endif  /* CONFIG_SYS_CLK_SPREAD */
 102
 103/*
 104 * Prosessor Bus Clock (in MHz) defined by CG_PB_SELECT
 105 * (based on recommended Tsi108 reference clock 33MHz)
 106 */
 107static int pb_clk_sel[8] = { 0, 0, 183, 100, 133, 167, 200, 233 };
 108
 109/*
 110 * get_board_bus_clk ()
 111 *
 112 * returns the bus clock in Hz.
 113 */
 114unsigned long get_board_bus_clk (void)
 115{
 116        ulong i;
 117
 118        /* Detect PB clock freq. */
 119        i = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS);
 120        i = (i >> 16) & 0x07;   /* Get PB PLL multiplier */
 121
 122        return pb_clk_sel[i] * 1000000;
 123}
 124
 125/*
 126 * board_early_init_f ()
 127 *
 128 * board-specific initialization executed from flash
 129 */
 130
 131int board_early_init_f (void)
 132{
 133        ulong i;
 134
 135        gd->mem_clk = 0;
 136        i = in32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET +
 137                        CG_PWRUP_STATUS);
 138        i = (i >> 20) & 0x07;   /* Get GD PLL multiplier */
 139        switch (i) {
 140        case 0: /* external clock */
 141                printf ("Using external clock\n");
 142                break;
 143        case 1: /* system clock */
 144                gd->mem_clk = gd->bus_clk;
 145                break;
 146        case 4: /* 133 MHz */
 147        case 5: /* 166 MHz */
 148        case 6: /* 200 MHz */
 149                gd->mem_clk = pb_clk_sel[i] * 1000000;
 150                break;
 151        default:
 152                printf ("Invalid DDR2 clock setting\n");
 153                return -1;
 154        }
 155        printf ("BUS: %lu MHz\n", get_board_bus_clk() / 1000000);
 156        printf ("MEM: %lu MHz\n", gd->mem_clk / 1000000);
 157        return 0;
 158}
 159
 160/*
 161 * board_early_init_r() - Tsi108 initialization function executed right after
 162 * relocation. Contains code that cannot be executed from flash.
 163 */
 164
 165int board_early_init_r (void)
 166{
 167        ulong temp, i;
 168        ulong reg_val;
 169        volatile ulong *reg_ptr;
 170
 171        reg_ptr =
 172                (ulong *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x900);
 173
 174        for (i = 0; i < 32; i++) {
 175                *reg_ptr++ = 0x00000201;        /* SWAP ENABLED */
 176                *reg_ptr++ = 0x00;
 177        }
 178
 179        __asm__ __volatile__ ("eieio");
 180        __asm__ __volatile__ ("sync");
 181
 182        /* Setup PB_OCN_BAR2: size 256B + ENable @ 0x0_80000000 */
 183
 184        out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2,
 185                0x80000001);
 186        __asm__ __volatile__ ("sync");
 187
 188        /* Make sure that OCN_BAR2 decoder is set (to allow following immediate
 189         * read from SDRAM)
 190         */
 191
 192        temp = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2);
 193        __asm__ __volatile__ ("sync");
 194
 195        /*
 196         * Remap PB_OCN_BAR1 to accomodate PCI-bus aperture and EPROM into the
 197         * processor bus address space. Immediately after reset LUT and address
 198         * translation are disabled for this BAR. Now we have to initialize LUT
 199         * and switch from the BOOT mode to the normal operation mode.
 200         *
 201         * The aperture defined by PB_OCN_BAR1 startes at address 0xE0000000
 202         * and covers 512MB of address space. To allow larger aperture we also
 203         * have to relocate register window of Tsi108
 204         *
 205         * Initialize LUT (32-entries) prior switching PB_OCN_BAR1 from BOOT
 206         * mode.
 207         *
 208         * initialize pointer to LUT associated with PB_OCN_BAR1
 209         */
 210        reg_ptr =
 211                (ulong *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x800);
 212
 213        for (i = 0; i < 32; i++) {
 214                *reg_ptr++ = pb2ocn_lut1[i].lower;
 215                *reg_ptr++ = pb2ocn_lut1[i].upper;
 216        }
 217
 218        __asm__ __volatile__ ("sync");
 219
 220        /* Base addresses for CS0, CS1, CS2, CS3 */
 221
 222        out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_ADDR,
 223                0x00000000);
 224        __asm__ __volatile__ ("sync");
 225
 226        out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_ADDR,
 227                0x00100000);
 228        __asm__ __volatile__ ("sync");
 229
 230        out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_ADDR,
 231                0x00200000);
 232        __asm__ __volatile__ ("sync");
 233
 234        out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_ADDR,
 235                0x00300000);
 236        __asm__ __volatile__ ("sync");
 237
 238        /* Masks for HLP banks */
 239
 240        out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_MASK,
 241                0xFFF00000);
 242        __asm__ __volatile__ ("sync");
 243
 244        out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_MASK,
 245                0xFFF00000);
 246        __asm__ __volatile__ ("sync");
 247
 248        out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_MASK,
 249                0xFFF00000);
 250        __asm__ __volatile__ ("sync");
 251
 252        out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_MASK,
 253                0xFFF00000);
 254        __asm__ __volatile__ ("sync");
 255
 256        /* Set CTRL0 values for banks */
 257
 258        out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL0,
 259                0x7FFC44C2);
 260        __asm__ __volatile__ ("sync");
 261
 262        out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL0,
 263                0x7FFC44C0);
 264        __asm__ __volatile__ ("sync");
 265
 266        out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL0,
 267                0x7FFC44C0);
 268        __asm__ __volatile__ ("sync");
 269
 270        out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL0,
 271                0x7FFC44C2);
 272        __asm__ __volatile__ ("sync");
 273
 274        /* Set banks to latched mode, enabled, and other default settings */
 275
 276        out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL1,
 277                0x7C0F2000);
 278        __asm__ __volatile__ ("sync");
 279
 280        out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL1,
 281                0x7C0F2000);
 282        __asm__ __volatile__ ("sync");
 283
 284        out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL1,
 285                0x7C0F2000);
 286        __asm__ __volatile__ ("sync");
 287
 288        out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL1,
 289                0x7C0F2000);
 290        __asm__ __volatile__ ("sync");
 291
 292        /*
 293         * Set new value for PB_OCN_BAR1: switch from BOOT to LUT mode.
 294         * value for PB_OCN_BAR1: (BA-0xE000_0000 + size 512MB + ENable)
 295         */
 296        out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1,
 297                0xE0000011);
 298        __asm__ __volatile__ ("sync");
 299
 300        /* Make sure that OCN_BAR2 decoder is set (to allow following
 301         * immediate read from SDRAM)
 302         */
 303
 304        temp = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1);
 305        __asm__ __volatile__ ("sync");
 306
 307        /*
 308         * SRI: At this point we have enabled the HLP banks. That means we can
 309         * now read from the NVRAM and initialize the environment variables.
 310         * We will over-ride the env_init called in board_init_f
 311         * This is really a work-around because, the HLP bank 1
 312         * where NVRAM resides is not visible during board_init_f
 313         * (arch/powerpc/lib/board.c)
 314         * Alternatively, we could use the I2C EEPROM at start-up to configure
 315         * and enable all HLP banks and not just HLP 0 as is being done for
 316         * Taiga Rev. 2.
 317         */
 318
 319        env_init ();
 320
 321#ifndef DISABLE_PBM
 322
 323        /*
 324         * For IBM processors we have to set Address-Only commands generated
 325         * by PBM that are different from ones set after reset.
 326         */
 327
 328        temp = get_cpu_type ();
 329
 330        if ((CPU_750FX == temp) || (CPU_750GX == temp))
 331                out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_MCMD,
 332                        0x00009955);
 333#endif  /* DISABLE_PBM */
 334
 335#ifdef CONFIG_PCI
 336        /*
 337         * Initialize PCI/X block
 338         */
 339
 340        /* Map PCI/X Configuration Space (16MB @ 0x0_FE000000) */
 341        out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET +
 342                PCI_PFAB_BAR0_UPPER, 0);
 343        __asm__ __volatile__ ("sync");
 344
 345        out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_BAR0,
 346                0xFB000001);
 347        __asm__ __volatile__ ("sync");
 348
 349        /* Set Bus Number for the attached PCI/X bus (we will use 0 for NB) */
 350
 351        temp =  in32(CONFIG_SYS_TSI108_CSR_BASE +
 352                TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT);
 353
 354        temp &= ~0xFF00;        /* Clear the BUS_NUM field */
 355
 356        out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT,
 357                temp);
 358
 359        /* Map PCI/X IO Space (64KB @ 0x0_FD000000) takes one 16MB LUT entry */
 360
 361        out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO_UPPER,
 362                0);
 363        __asm__ __volatile__ ("sync");
 364
 365        /* This register is on the PCI side to interpret the address it receives
 366         * and maps it as a IO address.
 367         */
 368
 369        out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO,
 370                0x00000001);
 371        __asm__ __volatile__ ("sync");
 372
 373        /*
 374         * Map PCI/X Memory Space
 375         *
 376         * Transactions directed from OCM to PCI Memory Space are directed
 377         * from PB to PCI
 378         * unchanged (as defined by PB_OCN_BAR1,2 and LUT settings).
 379         * If address remapping is required the corresponding PCI_PFAB_MEM32
 380         * and PCI_PFAB_PFMx register groups have to be configured.
 381         *
 382         * Map the path from the PCI/X bus into the system memory
 383         *
 384         * The memory mapped window assotiated with PCI P2O_BAR2 provides
 385         * access to the system memory without address remapping.
 386         * All system memory is opened for accesses initiated by PCI/X bus
 387         * masters.
 388         *
 389         * Initialize LUT associated with PCI P2O_BAR2
 390         *
 391         * set pointer to LUT associated with PCI P2O_BAR2
 392         */
 393
 394        reg_ptr =
 395                (ulong *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x500);
 396
 397#ifdef DISABLE_PBM
 398
 399        /* In case when PBM is disabled (no HW supported cache snoopng on PB)
 400         * P2O_BAR2 is directly mapped into the system memory without address
 401         * translation.
 402         */
 403
 404        reg_val = 0x00000004;   /* SDRAM port + NO Addr_Translation */
 405
 406        for (i = 0; i < 32; i++) {
 407                *reg_ptr++ = reg_val;   /* P2O_BAR2_LUTx */
 408                *reg_ptr++ = 0;         /* P2O_BAR2_LUT_UPPERx */
 409        }
 410
 411        /* value for PCI BAR2 (size = 512MB, Enabled, No Addr. Translation) */
 412        reg_val = 0x00007500;
 413#else
 414
 415        reg_val = 0x00000002;   /* Destination port = PBM */
 416
 417        for (i = 0; i < 32; i++) {
 418                *reg_ptr++ = reg_val;   /* P2O_BAR2_LUTx */
 419/* P2O_BAR2_LUT_UPPERx : Set data swapping mode for PBM (byte swapping) */
 420                *reg_ptr++ = 0x40000000;
 421/* offset = 16MB, address translation is enabled to allow byte swapping */
 422                reg_val += 0x01000000;
 423        }
 424
 425/* value for PCI BAR2 (size = 512MB, Enabled, Address Translation Enabled) */
 426        reg_val = 0x00007100;
 427#endif
 428
 429        __asm__ __volatile__ ("eieio");
 430        __asm__ __volatile__ ("sync");
 431
 432        out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES,
 433                reg_val);
 434        __asm__ __volatile__ ("sync");
 435
 436        /* Set 64-bit PCI bus address for system memory
 437         * ( 0 is the best choice for easy mapping)
 438         */
 439
 440        out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2,
 441                0x00000000);
 442        out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2_UPPER,
 443                0x00000000);
 444        __asm__ __volatile__ ("sync");
 445
 446#ifndef DISABLE_PBM
 447        /*
 448         *  The memory mapped window assotiated with PCI P2O_BAR3 provides
 449         *  access to the system memory using SDRAM OCN port and address
 450         *  translation. This is alternative way to access SDRAM from PCI
 451         *  required for Tsi108 emulation testing.
 452         *  All system memory is opened for accesses initiated by
 453         *  PCI/X bus masters.
 454         *
 455         *  Initialize LUT associated with PCI P2O_BAR3
 456         *
 457         *  set pointer to LUT associated with PCI P2O_BAR3
 458         */
 459        reg_ptr =
 460                (ulong *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x600);
 461
 462        reg_val = 0x00000004;   /* Destination port = SDC */
 463
 464        for (i = 0; i < 32; i++) {
 465                *reg_ptr++ = reg_val;   /* P2O_BAR3_LUTx */
 466
 467/* P2O_BAR3_LUT_UPPERx : Set data swapping mode for PBM (byte swapping) */
 468                *reg_ptr++ = 0;
 469
 470/* offset = 16MB, address translation is enabled to allow byte swapping */
 471                reg_val += 0x01000000;
 472        }
 473
 474        __asm__ __volatile__ ("eieio");
 475        __asm__ __volatile__ ("sync");
 476
 477        /* Configure PCI P2O_BAR3 (size = 512MB, Enabled) */
 478
 479        reg_val =
 480                in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET +
 481                 PCI_P2O_PAGE_SIZES);
 482        reg_val &= ~0x00FF;
 483        reg_val |= 0x0071;
 484        out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES,
 485                reg_val);
 486        __asm__ __volatile__ ("sync");
 487
 488        /* Set 64-bit base PCI bus address for window (0x20000000) */
 489
 490        out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3_UPPER,
 491                0x00000000);
 492        out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3,
 493                0x20000000);
 494        __asm__ __volatile__ ("sync");
 495
 496#endif  /* !DISABLE_PBM */
 497
 498#ifdef ENABLE_PCI_CSR_BAR
 499        /* open if required access to Tsi108 CSRs from the PCI/X bus */
 500        /* enable BAR0 on the PCI/X bus */
 501        reg_val = in32(CONFIG_SYS_TSI108_CSR_BASE +
 502                TSI108_PCI_REG_OFFSET + PCI_MISC_CSR);
 503        reg_val |= 0x02;
 504        out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_MISC_CSR,
 505                reg_val);
 506        __asm__ __volatile__ ("sync");
 507
 508        out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0_UPPER,
 509                0x00000000);
 510        out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0,
 511                CONFIG_SYS_TSI108_CSR_BASE);
 512        __asm__ __volatile__ ("sync");
 513
 514#endif
 515
 516        /*
 517         * Finally enable PCI/X Bus Master and Memory Space access
 518         */
 519
 520        reg_val = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR);
 521        reg_val |= 0x06;
 522        out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR, reg_val);
 523        __asm__ __volatile__ ("sync");
 524
 525#endif  /* CONFIG_PCI */
 526
 527        /*
 528         * Initialize MPIC outputs (interrupt pins):
 529         * Interrupt routing on the Grendel Emul. Board:
 530         * PB_INT[0] -> INT (CPU0)
 531         * PB_INT[1] -> INT (CPU1)
 532         * PB_INT[2] -> MCP (CPU0)
 533         * PB_INT[3] -> MCP (CPU1)
 534         * Set interrupt controller outputs as Level_Sensitive/Active_Low
 535         */
 536        out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(0), 0x02);
 537        out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(1), 0x02);
 538        out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(2), 0x02);
 539        out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(3), 0x02);
 540        __asm__ __volatile__ ("sync");
 541
 542        /*
 543         * Ensure that Machine Check exception is enabled
 544         * We need it to support PCI Bus probing (configuration reads)
 545         */
 546
 547        reg_val = mfmsr ();
 548        mtmsr(reg_val | MSR_ME);
 549
 550        return 0;
 551}
 552
 553/*
 554 * Needed to print out L2 cache info
 555 * used in the misc_init_r function
 556 */
 557
 558unsigned long get_l2cr (void)
 559{
 560        unsigned long l2controlreg;
 561        asm volatile ("mfspr %0, 1017":"=r" (l2controlreg):);
 562        return l2controlreg;
 563}
 564
 565/*
 566 * misc_init_r()
 567 *
 568 * various things to do after relocation
 569 *
 570 */
 571
 572int misc_init_r (void)
 573{
 574#ifdef CONFIG_SYS_CLK_SPREAD    /* Initialize Spread-Spectrum Clock generation */
 575        ulong i;
 576
 577        /* Ensure that Spread-Spectrum is disabled */
 578        out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, 0);
 579        out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, 0);
 580
 581        /* Initialize PLL1: CG_PCI_CLK , internal OCN_CLK
 582         * Uses pre-calculated value for Fout = 800 MHz, Fs = 30 kHz, D = 0.5%
 583         */
 584
 585        out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0,
 586                0x002e0044);    /* D = 0.25% */
 587        out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL1,
 588                0x00000039);    /* BWADJ */
 589
 590        /* Initialize PLL0: CG_PB_CLKO  */
 591        /* Detect PB clock freq. */
 592        i = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS);
 593        i = (i >> 16) & 0x07;   /* Get PB PLL multiplier */
 594
 595        out32 (CONFIG_SYS_TSI108_CSR_BASE +
 596                TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, pll0_config[i].ctrl0);
 597        out32 (CONFIG_SYS_TSI108_CSR_BASE +
 598                TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL1, pll0_config[i].ctrl1);
 599
 600        /* Wait and set SSEN for both PLL0 and 1 */
 601        udelay (1000);
 602        out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0,
 603                0x802e0044);    /* D=0.25% */
 604        out32 (CONFIG_SYS_TSI108_CSR_BASE +
 605                TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0,
 606                0x80000000 | pll0_config[i].ctrl0);
 607#endif  /* CONFIG_SYS_CLK_SPREAD */
 608
 609#ifdef CONFIG_SYS_L2
 610        l2cache_enable ();
 611#endif
 612        printf ("BUS:   %lu MHz\n", gd->bus_clk / 1000000);
 613        printf ("MEM:   %lu MHz\n", gd->mem_clk / 1000000);
 614
 615        /*
 616         * All the information needed to print the cache details is avaiblable
 617         * at this point i.e. above call to l2cache_enable is the very last
 618         * thing done with regards to enabling diabling the cache.
 619         * So this seems like a good place to print all this information
 620         */
 621
 622        printf ("CACHE: ");
 623        switch (get_cpu_type()) {
 624        case CPU_7447A:
 625                printf ("L1 Instruction cache - 32KB 8-way");
 626                (get_hid0 () & (1 << 15)) ? printf (" ENABLED\n") :
 627                        printf (" DISABLED\n");
 628                printf ("L1 Data cache - 32KB 8-way");
 629                (get_hid0 () & (1 << 14)) ? printf (" ENABLED\n") :
 630                        printf (" DISABLED\n");
 631                printf ("Unified L2 cache - 512KB 8-way");
 632                (get_l2cr () & (1 << 31)) ? printf (" ENABLED\n") :
 633                        printf (" DISABLED\n");
 634                printf ("\n");
 635                break;
 636
 637        case CPU_7448:
 638                printf ("L1 Instruction cache - 32KB 8-way");
 639                (get_hid0 () & (1 << 15)) ? printf (" ENABLED\n") :
 640                        printf (" DISABLED\n");
 641                printf ("L1 Data cache - 32KB 8-way");
 642                (get_hid0 () & (1 << 14)) ? printf (" ENABLED\n") :
 643                        printf (" DISABLED\n");
 644                printf ("Unified L2 cache - 1MB 8-way");
 645                (get_l2cr () & (1 << 31)) ? printf (" ENABLED\n") :
 646                        printf (" DISABLED\n");
 647                break;
 648        default:
 649                break;
 650        }
 651        return 0;
 652}
 653