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10#include <asm/mmu.h>
11#include <asm/io.h>
12#include <common.h>
13#include <mpc83xx.h>
14#include <pci.h>
15#include <i2c.h>
16#include <asm/fsl_i2c.h>
17#include "../common/pq-mds-pib.h"
18
19DECLARE_GLOBAL_DATA_PTR;
20
21static struct pci_region pci1_regions[] = {
22 {
23 bus_start: CONFIG_SYS_PCI1_MEM_BASE,
24 phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
25 size: CONFIG_SYS_PCI1_MEM_SIZE,
26 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
27 },
28 {
29 bus_start: CONFIG_SYS_PCI1_IO_BASE,
30 phys_start: CONFIG_SYS_PCI1_IO_PHYS,
31 size: CONFIG_SYS_PCI1_IO_SIZE,
32 flags: PCI_REGION_IO
33 },
34 {
35 bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
36 phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
37 size: CONFIG_SYS_PCI1_MMIO_SIZE,
38 flags: PCI_REGION_MEM
39 },
40};
41
42#ifdef CONFIG_MPC83XX_PCI2
43static struct pci_region pci2_regions[] = {
44 {
45 bus_start: CONFIG_SYS_PCI2_MEM_BASE,
46 phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
47 size: CONFIG_SYS_PCI2_MEM_SIZE,
48 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
49 },
50 {
51 bus_start: CONFIG_SYS_PCI2_IO_BASE,
52 phys_start: CONFIG_SYS_PCI2_IO_PHYS,
53 size: CONFIG_SYS_PCI2_IO_SIZE,
54 flags: PCI_REGION_IO
55 },
56 {
57 bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
58 phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
59 size: CONFIG_SYS_PCI2_MMIO_SIZE,
60 flags: PCI_REGION_MEM
61 },
62};
63#endif
64
65void pci_init_board(void)
66#ifdef CONFIG_PCISLAVE
67{
68 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
69 volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
70 volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0];
71 struct pci_region *reg[] = { pci1_regions };
72
73
74 pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
75 pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
76
77 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
78 pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
79
80 mpc83xx_pci_init(1, reg);
81
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83
84
85 pci_ctrl[0].pitar0 = 0x0;
86 pci_ctrl[0].pibar0 = 0x0;
87 pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP |
88 PIWAR_WTT_SNOOP | PIWAR_IWS_4K;
89
90 pci_ctrl[0].pitar1 = 0x0;
91 pci_ctrl[0].pibar1 = 0x0;
92 pci_ctrl[0].piebar1 = 0x0;
93 pci_ctrl[0].piwar1 &= ~PIWAR_EN;
94
95 pci_ctrl[0].pitar2 = 0x0;
96 pci_ctrl[0].pibar2 = 0x0;
97 pci_ctrl[0].piebar2 = 0x0;
98 pci_ctrl[0].piwar2 &= ~PIWAR_EN;
99
100
101 mpc83xx_pcislave_unlock(0);
102 printf("PCI: Agent mode enabled\n");
103}
104#else
105{
106 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
107 volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
108 volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
109#ifndef CONFIG_MPC83XX_PCI2
110 struct pci_region *reg[] = { pci1_regions };
111#else
112 struct pci_region *reg[] = { pci1_regions, pci2_regions };
113#endif
114
115
116 pib_init();
117
118#if defined(CONFIG_PCI_66M)
119 clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
120 printf("PCI clock is 66MHz\n");
121#elif defined(CONFIG_PCI_33M)
122 clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 |
123 OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR;
124 printf("PCI clock is 33MHz\n");
125#else
126 clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
127 printf("PCI clock is 66MHz\n");
128#endif
129 udelay(2000);
130
131
132 pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
133 pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
134
135 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
136 pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;
137
138 udelay(2000);
139
140#ifndef CONFIG_MPC83XX_PCI2
141 mpc83xx_pci_init(1, reg);
142#else
143 mpc83xx_pci_init(2, reg);
144#endif
145}
146#endif
147