LXR uboot/board/gen860t/gen860t.c

   1/*
   2 * (C) Copyright 2000
   3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4 * Keith Outwater, keith_outwater@mvis.com
   5 *
   6 * SPDX-License-Identifier:     GPL-2.0+
   7 */
   8
   9#include <virtex2.h>
  10#include <common.h>
  11#include <mpc8xx.h>
  12#include <asm/8xx_immap.h>
  13#include "beeper.h"
  14#include "fpga.h"
  15#include "ioport.h"
  16
  17DECLARE_GLOBAL_DATA_PTR;
  18
  19#ifdef CONFIG_STATUS_LED
  20#include <status_led.h>
  21#endif
  22
  23#if defined(CONFIG_CMD_MII) && defined(CONFIG_MII)
  24#include <net.h>
  25#endif
  26
  27#if 0
  28#define GEN860T_DEBUG
  29#endif
  30
  31#ifdef GEN860T_DEBUG
  32#define PRINTF(fmt,args...)     printf (fmt ,##args)
  33#else
  34#define PRINTF(fmt,args...)
  35#endif
  36
  37/*
  38 * The following UPM init tables were generated automatically by
  39 * Motorola's MCUINIT program. See the README file for UPM to
  40 * SDRAM pin assignments if you want to type this data into
  41 * MCUINIT in order to reverse engineer the waveforms.
  42 */
  43
  44/*
  45 * UPM initialization tables for MICRON MT48LC16M16A2TG SDRAM devices
  46 * (UPMA) and Virtex FPGA SelectMap interface (UPMB).
  47 * NOTE that unused areas of the table are used to hold NOP, precharge
  48 * and mode register set sequences.
  49 *
  50 */
  51#define UPMA_NOP_ADDR                   0x5
  52#define UPMA_PRECHARGE_ADDR             0x6
  53#define UPMA_MRS_ADDR                   0x12
  54
  55#define UPM_SINGLE_READ_ADDR    0x00
  56#define UPM_BURST_READ_ADDR             0x08
  57#define UPM_SINGLE_WRITE_ADDR   0x18
  58#define UPM_BURST_WRITE_ADDR    0x20
  59#define UPM_REFRESH_ADDR                0x30
  60
  61const uint sdram_upm_table[] = {
  62        /* single read   (offset 0x00 in upm ram) */
  63        0x0e0fdc04, 0x01adfc04, 0x0fbffc00, 0x1fff5c05,
  64        0xffffffff, 0x0fffffcd, 0x0fff0fce, 0xefcfffff,
  65        /* burst read    (offset 0x08 in upm ram) */
  66        0x0f0fdc04, 0x00fdfc04, 0xf0fffc00, 0xf0fffc00,
  67        0xf1fffc00, 0xfffffc00, 0xfffffc05, 0xffffffff,
  68        0xffffffff, 0xffffffff, 0x0ffffff4, 0x1f3d5ff4,
  69        0xfffffff4, 0xfffffff5, 0xffffffff, 0xffffffff,
  70        /* single write  (offset 0x18 in upm ram) */
  71        0x0f0fdc04, 0x00ad3c00, 0x1fff5c05, 0xffffffff,
  72        0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  73        /* burst write   (offset 0x20 in upm ram) */
  74        0x0f0fdc00, 0x10fd7c00, 0xf0fffc00, 0xf0fffc00,
  75        0xf1fffc04, 0xfffffc05, 0xffffffff, 0xffffffff,
  76        0xffffffff, 0xffffffff, 0xffffffff, 0xfffff7ff,
  77        0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  78        /* refresh       (offset 0x30 in upm ram) */
  79        0x1ffddc84, 0xfffffc04, 0xfffffc04, 0xfffffc84,
  80        0xfffffc05, 0xffffffff, 0xffffffff, 0xffffffff,
  81        0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  82        /* exception     (offset 0x3C in upm ram) */
  83};
  84
  85const uint selectmap_upm_table[] = {
  86        /* single read   (offset 0x00 in upm ram) */
  87        0x88fffc06, 0x00fff404, 0x00fffc04, 0x33fffc00,
  88        0xfffffc05, 0xffffffff, 0xffffffff, 0xffffffff,
  89        /* burst read    (offset 0x08 in upm ram) */
  90        0xfffffc04, 0xfffffc05, 0xffffffff, 0xffffffff,
  91        0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  92        0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  93        0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  94        /* single write  (offset 0x18 in upm ram) */
  95        0x88fffc04, 0x00fff400, 0x77fffc05, 0xffffffff,
  96        0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  97        /* burst write   (offset 0x20 in upm ram) */
  98        0xfffffc04, 0xfffffc05, 0xffffffff, 0xffffffff,
  99        0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
 100        0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
 101        0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
 102        /* refresh       (offset 0x30 in upm ram) */
 103        0xfffffc04, 0xfffffc05, 0xffffffff, 0xffffffff,
 104        0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
 105        0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
 106        /* exception     (offset 0x3C in upm ram) */
 107        0xfffffc05, 0xffffffff, 0xffffffff, 0xffffffff
 108};
 109
 110/*
 111 * Check board identity.  Always successful (gives information only)
 112 */
 113int checkboard (void)
 114{
 115        char *s;
 116        char buf[64];
 117        int i;
 118
 119        i = getenv_f("board_id", buf, sizeof (buf));
 120        s = (i > 0) ? buf : NULL;
 121
 122        if (s) {
 123                printf ("%s ", s);
 124        } else {
 125                printf ("<unknown> ");
 126        }
 127
 128        i = getenv_f("serial#", buf, sizeof (buf));
 129        s = (i > 0) ? buf : NULL;
 130
 131        if (s) {
 132                printf ("S/N %s\n", s);
 133        } else {
 134                printf ("S/N <unknown>\n");
 135        }
 136
 137        printf ("CPU at %s MHz, ", strmhz (buf, gd->cpu_clk));
 138        printf ("local bus at %s MHz\n", strmhz (buf, gd->bus_clk));
 139        return (0);
 140}
 141
 142/*
 143 * Initialize SDRAM
 144 */
 145phys_size_t initdram (int board_type)
 146{
 147        volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 148        volatile memctl8xx_t *memctl = &immr->im_memctl;
 149
 150        upmconfig (UPMA,
 151                   (uint *) sdram_upm_table,
 152                   sizeof (sdram_upm_table) / sizeof (uint)
 153                );
 154
 155        /*
 156         * Setup MAMR register
 157         */
 158        memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_8K;
 159        memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE));      /* no refresh yet */
 160
 161        /*
 162         * Map CS1* to SDRAM bank
 163         */
 164        memctl->memc_or1 = CONFIG_SYS_OR1;
 165        memctl->memc_br1 = CONFIG_SYS_BR1;
 166
 167        /*
 168         * Perform SDRAM initialization sequence:
 169         * 1. Apply at least one NOP command
 170         * 2. 100 uS delay (JEDEC standard says 200 uS)
 171         * 3. Issue 4 precharge commands
 172         * 4. Perform two refresh cycles
 173         * 5. Program mode register
 174         *
 175         * Program SDRAM for standard operation, sequential burst, burst length
 176         * of 4, CAS latency of 2.
 177         */
 178        memctl->memc_mar = 0x00000000;
 179        memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
 180                MCR_MLCF (0) | UPMA_NOP_ADDR;
 181        udelay (200);
 182        memctl->memc_mar = 0x00000000;
 183        memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
 184                MCR_MLCF (4) | UPMA_PRECHARGE_ADDR;
 185
 186        memctl->memc_mar = 0x00000000;
 187        memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
 188                MCR_MLCF (2) | UPM_REFRESH_ADDR;
 189
 190        memctl->memc_mar = 0x00000088;
 191        memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
 192                MCR_MLCF (1) | UPMA_MRS_ADDR;
 193
 194        memctl->memc_mar = 0x00000000;
 195        memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
 196                MCR_MLCF (0) | UPMA_NOP_ADDR;
 197        /*
 198         * Enable refresh
 199         */
 200        memctl->memc_mamr |= MAMR_PTAE;
 201
 202        return (SDRAM_SIZE);
 203}
 204
 205/*
 206 * Disk On Chip (DOC) Millenium initialization.
 207 * The DOC lives in the CS2* space
 208 */
 209#if defined(CONFIG_CMD_DOC)
 210void doc_init (void)
 211{
 212        printf ("Probing at 0x%.8x: ", DOC_BASE);
 213        doc_probe (DOC_BASE);
 214}
 215#endif
 216
 217/*
 218 * Miscellaneous intialization
 219 */
 220int misc_init_r (void)
 221{
 222        volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 223        volatile memctl8xx_t *memctl = &immr->im_memctl;
 224
 225        /*
 226         * Set up UPMB to handle the Virtex FPGA SelectMap interface
 227         */
 228        upmconfig (UPMB, (uint *) selectmap_upm_table,
 229                   sizeof (selectmap_upm_table) / sizeof (uint));
 230
 231        memctl->memc_mbmr = 0x0;
 232
 233        config_mpc8xx_ioports (immr);
 234
 235#if defined(CONFIG_CMD_MII)
 236        mii_init ();
 237#endif
 238
 239#if defined(CONFIG_FPGA)
 240        gen860t_init_fpga ();
 241#endif
 242        return 0;
 243}
 244
 245/*
 246 * Final init hook before entering command loop.
 247 */
 248int last_stage_init (void)
 249{
 250#if !defined(CONFIG_SC)
 251        char buf[256];
 252        int i;
 253
 254        /*
 255         * Turn the beeper volume all the way down in case this is a warm boot.
 256         */
 257        set_beeper_volume (-64);
 258        init_beeper ();
 259
 260        /*
 261         * Read the environment to see what to do with the beeper
 262         */
 263        i = getenv_f("beeper", buf, sizeof (buf));
 264        if (i > 0) {
 265                do_beeper (buf);
 266        }
 267#endif
 268        return 0;
 269}
 270
 271/*
 272 * Stub to make POST code happy.  Can't self-poweroff, so just hang.
 273 */
 274void board_poweroff (void)
 275{
 276        puts ("### Please power off the board ###\n");
 277        while (1);
 278}
 279