LXR uboot/board/matrix_vision/mvblm7/pci.c

   1/*
   2 * Copyright (C) Freescale Semiconductor, Inc. 2006.
   3 *
   4 * (C) Copyright 2008
   5 * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
   6 *
   7 * SPDX-License-Identifier:     GPL-2.0+
   8 */
   9
  10#include <common.h>
  11#if defined(CONFIG_OF_LIBFDT)
  12#include <libfdt.h>
  13#endif
  14#include <pci.h>
  15#include <mpc83xx.h>
  16#include <fpga.h>
  17#include "mvblm7.h"
  18#include "fpga.h"
  19#include "../common/mv_common.h"
  20
  21DECLARE_GLOBAL_DATA_PTR;
  22
  23static struct pci_region pci_regions[] = {
  24        {
  25                bus_start: CONFIG_SYS_PCI1_MEM_BASE,
  26                phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
  27                size: CONFIG_SYS_PCI1_MEM_SIZE,
  28                flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
  29        },
  30        {
  31                bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
  32                phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
  33                size: CONFIG_SYS_PCI1_MMIO_SIZE,
  34                flags: PCI_REGION_MEM
  35        },
  36        {
  37                bus_start: CONFIG_SYS_PCI1_IO_BASE,
  38                phys_start: CONFIG_SYS_PCI1_IO_PHYS,
  39                size: CONFIG_SYS_PCI1_IO_SIZE,
  40                flags: PCI_REGION_IO
  41        }
  42};
  43
  44void pci_init_board(void)
  45{
  46        int i;
  47        volatile immap_t *immr;
  48        volatile pcictrl83xx_t *pci_ctrl;
  49        volatile gpio83xx_t *gpio;
  50        volatile clk83xx_t *clk;
  51        volatile law83xx_t *pci_law;
  52        struct pci_region *reg[] = { pci_regions };
  53
  54        immr = (immap_t *) CONFIG_SYS_IMMR;
  55        clk = (clk83xx_t *) &immr->clk;
  56        pci_ctrl = immr->pci_ctrl;
  57        pci_law = immr->sysconf.pcilaw;
  58        gpio  = (volatile gpio83xx_t *)&immr->gpio[0];
  59
  60        gpio->dat = MV_GPIO_DAT;
  61        gpio->odr = MV_GPIO_ODE;
  62        gpio->dir = MV_GPIO_OUT;
  63
  64        printf("SICRH / SICRL : 0x%08x / 0x%08x\n", immr->sysconf.sicrh,
  65                immr->sysconf.sicrl);
  66
  67        mvblm7_init_fpga();
  68        mv_load_fpga();
  69
  70        gpio->dir = MV_GPIO_OUT & ~(FPGA_DIN|FPGA_CCLK);
  71
  72        /* Enable PCI_CLK_OUTPUTs 0 and 1 with 1:1 clocking */
  73        clk->occr = 0xc0000000;
  74
  75        pci_ctrl[0].gcr = 0;
  76        udelay(2000);
  77        pci_ctrl[0].gcr = 1;
  78
  79        for (i = 0; i < 1000; ++i)
  80                udelay(1000);
  81
  82        pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
  83        pci_law[0].ar = LBLAWAR_EN | LBLAWAR_1GB;
  84
  85        pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
  86        pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
  87
  88        mpc83xx_pci_init(1, reg);
  89}
  90