LXR uboot/board/prodrive/p3p440/p3p440.c

   1/*
   2 * (C) Copyright 2005
   3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4 *
   5 * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
   6 *
   7 * SPDX-License-Identifier:     GPL-2.0+
   8 */
   9
  10#include <common.h>
  11#include <asm/processor.h>
  12#include <command.h>
  13
  14#include "p3p440.h"
  15
  16DECLARE_GLOBAL_DATA_PTR;
  17
  18void set_led(int color)
  19{
  20        switch (color) {
  21        case LED_OFF:
  22                out32(GPIO0_OR,  in32(GPIO0_OR) & ~CONFIG_SYS_LED_GREEN & ~CONFIG_SYS_LED_RED);
  23                break;
  24
  25        case LED_GREEN:
  26                out32(GPIO0_OR,  (in32(GPIO0_OR) | CONFIG_SYS_LED_GREEN) & ~CONFIG_SYS_LED_RED);
  27                break;
  28
  29        case LED_RED:
  30                out32(GPIO0_OR,  (in32(GPIO0_OR) | CONFIG_SYS_LED_RED) & ~CONFIG_SYS_LED_GREEN);
  31                break;
  32
  33        case LED_ORANGE:
  34                out32(GPIO0_OR,  in32(GPIO0_OR) | CONFIG_SYS_LED_GREEN | CONFIG_SYS_LED_RED);
  35                break;
  36        }
  37}
  38
  39static int is_monarch(void)
  40{
  41        out32(GPIO0_OR,  in32(GPIO0_OR) & ~CONFIG_SYS_GPIO_RDY);
  42        udelay(1000);
  43
  44        if (in32(GPIO0_IR) & CONFIG_SYS_MONARCH_IO)
  45                return 0;
  46        else
  47                return 1;
  48}
  49
  50static void wait_for_pci_ready(void)
  51{
  52        /*
  53         * Configure EREADY_IO as input
  54         */
  55        out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CONFIG_SYS_EREADY_IO);
  56        udelay(1000);
  57
  58        for (;;) {
  59                if (in32(GPIO0_IR) & CONFIG_SYS_EREADY_IO)
  60                        return;
  61        }
  62
  63}
  64
  65int board_early_init_f(void)
  66{
  67        uint reg;
  68
  69        /*--------------------------------------------------------------------
  70         * Setup the external bus controller/chip selects
  71         *-------------------------------------------------------------------*/
  72        mtdcr(EBC0_CFGADDR, EBC0_CFG);
  73        reg = mfdcr(EBC0_CFGDATA);
  74        mtdcr(EBC0_CFGDATA, reg | 0x04000000);  /* Set ATC */
  75
  76        /*--------------------------------------------------------------------
  77         * Setup pin multiplexing (GPIO/IRQ...)
  78         *-------------------------------------------------------------------*/
  79        mtdcr(CPC0_GPIO, 0x03F01F80);
  80
  81        out32(GPIO0_ODR, 0x00000000);   /* no open drain pins      */
  82        out32(GPIO0_TCR, CONFIG_SYS_GPIO_RDY | CONFIG_SYS_EREADY_IO | CONFIG_SYS_LED_RED | CONFIG_SYS_LED_GREEN);
  83        out32(GPIO0_OR,  CONFIG_SYS_GPIO_RDY);
  84
  85        /*--------------------------------------------------------------------
  86         * Setup the interrupt controller polarities, triggers, etc.
  87         *-------------------------------------------------------------------*/
  88        mtdcr(UIC0SR, 0xffffffff);      /* clear all */
  89        mtdcr(UIC0ER, 0x00000000);      /* disable all */
  90        mtdcr(UIC0CR, 0x00000001);      /* UIC1 crit is critical */
  91        mtdcr(UIC0PR, 0xfffffe13);      /* per ref-board manual */
  92        mtdcr(UIC0TR, 0x01c00008);      /* per ref-board manual */
  93        mtdcr(UIC0VR, 0x00000001);      /* int31 highest, base=0x000 */
  94        mtdcr(UIC0SR, 0xffffffff);      /* clear all */
  95
  96        mtdcr(UIC1SR, 0xffffffff);      /* clear all */
  97        mtdcr(UIC1ER, 0x00000000);      /* disable all */
  98        mtdcr(UIC1CR, 0x00000000);      /* all non-critical */
  99        mtdcr(UIC1PR, 0xffffe0ff);      /* per ref-board manual */
 100        mtdcr(UIC1TR, 0x00ffc000);      /* per ref-board manual */
 101        mtdcr(UIC1VR, 0x00000001);      /* int31 highest, base=0x000 */
 102        mtdcr(UIC1SR, 0xffffffff);      /* clear all */
 103
 104        return 0;
 105}
 106
 107int checkboard(void)
 108{
 109        char buf[64];
 110        int i = getenv_f("serial#", buf, sizeof(buf));
 111
 112        printf("Board: P3P440");
 113        if (i > 0) {
 114                puts(", serial# ");
 115                puts(buf);
 116        }
 117
 118        if (is_monarch()) {
 119                puts(", Monarch");
 120        } else {
 121                puts(", None-Monarch");
 122        }
 123
 124        putc('\n');
 125
 126        return (0);
 127}
 128
 129int misc_init_r (void)
 130{
 131        /*
 132         * Adjust flash start and offset to detected values
 133         */
 134        gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
 135        gd->bd->bi_flashoffset = 0;
 136
 137        /*
 138         * Check if only one FLASH bank is available
 139         */
 140        if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) {
 141                mtebc(PB1CR, 0);                        /* disable cs */
 142                mtebc(PB1AP, 0);
 143                mtebc(PB2CR, 0);                        /* disable cs */
 144                mtebc(PB2AP, 0);
 145                mtebc(PB3CR, 0);                        /* disable cs */
 146                mtebc(PB3AP, 0);
 147        }
 148
 149        return 0;
 150}
 151
 152/*************************************************************************
 153 * Override weak is_pci_host()
 154 *
 155 *      This routine is called to determine if a pci scan should be
 156 *      performed. With various hardware environments (especially cPCI and
 157 *      PPMC) it's insufficient to depend on the state of the arbiter enable
 158 *      bit in the strap register, or generic host/adapter assumptions.
 159 *
 160 *      Rather than hard-code a bad assumption in the general 440 code, the
 161 *      440 pci code requires the board to decide at runtime.
 162 *
 163 *      Return 0 for adapter mode, non-zero for host (monarch) mode.
 164 *
 165 *
 166 ************************************************************************/
 167#if defined(CONFIG_PCI)
 168int is_pci_host(struct pci_controller *hose)
 169{
 170        if (is_monarch()) {
 171                wait_for_pci_ready();
 172                return 1;               /* return 1 for host controller */
 173        } else {
 174                return 0;               /* return 0 for adapter controller */
 175        }
 176}
 177#endif                          /* defined(CONFIG_PCI) */
 178