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16#include <common.h>
17#include <errno.h>
18#include <spl.h>
19#include <asm/arch/cpu.h>
20#include <asm/arch/hardware.h>
21#include <asm/arch/omap.h>
22#include <asm/arch/ddr_defs.h>
23#include <asm/arch/clock.h>
24#include <asm/arch/gpio.h>
25#include <asm/arch/mmc_host_def.h>
26#include <asm/arch/sys_proto.h>
27#include <asm/io.h>
28#include <asm/emif.h>
29#include <asm/gpio.h>
30#include <i2c.h>
31#include <miiphy.h>
32#include <cpsw.h>
33#include <watchdog.h>
34#include "board.h"
35#include "../common/factoryset.h"
36
37DECLARE_GLOBAL_DATA_PTR;
38
39#ifdef CONFIG_SPL_BUILD
40static struct dxr2_baseboard_id __attribute__((section(".data"))) settings;
41
42const struct ddr3_data ddr3_default = {
43 0x33524444, 0x56312e34, 0x0080, 0x0000, 0x0038, 0x003E, 0x00A4,
44 0x0075, 0x0888A39B, 0x26247FDA, 0x501F821F, 0x00100206, 0x61A44A32,
45 0x00000618, 0x0000014A,
46};
47
48static void set_default_ddr3_timings(void)
49{
50 printf("Set default DDR3 settings\n");
51 settings.ddr3 = ddr3_default;
52}
53
54static void print_ddr3_timings(void)
55{
56 printf("\n\nDDR3 Timing parameters:\n");
57 printf("Diff Eeprom Default\n");
58 PRINTARGS(magic);
59 PRINTARGS(version);
60 PRINTARGS(ddr3_sratio);
61 PRINTARGS(iclkout);
62
63 PRINTARGS(dt0rdsratio0);
64 PRINTARGS(dt0wdsratio0);
65 PRINTARGS(dt0fwsratio0);
66 PRINTARGS(dt0wrsratio0);
67
68 PRINTARGS(sdram_tim1);
69 PRINTARGS(sdram_tim2);
70 PRINTARGS(sdram_tim3);
71
72 PRINTARGS(emif_ddr_phy_ctlr_1);
73
74 PRINTARGS(sdram_config);
75 PRINTARGS(ref_ctrl);
76 PRINTARGS(ioctr_val);
77}
78
79static void print_chip_data(void)
80{
81 printf("\n");
82 printf("Device: '%s'\n", settings.chip.sdevname);
83 printf("HW version: '%s'\n", settings.chip.shwver);
84}
85#endif
86
87
88
89
90static int read_eeprom(void)
91{
92
93 if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
94 printf("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n");
95 return 1;
96 }
97
98#ifdef CONFIG_SPL_BUILD
99
100 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_DDR3, 2,
101 (uchar *)&settings.ddr3, sizeof(struct ddr3_data))) {
102 printf("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\nUse default DDR3 timings\n");
103 set_default_ddr3_timings();
104 }
105
106 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_CHIP, 2,
107 (uchar *)&settings.chip, sizeof(settings.chip)))
108 printf("Could not read chip settings\n");
109
110 if (ddr3_default.magic == settings.ddr3.magic &&
111 ddr3_default.version == settings.ddr3.version) {
112 printf("Using DDR3 settings from EEPROM\n");
113 } else {
114 if (ddr3_default.magic != settings.ddr3.magic)
115 printf("Error: No valid DDR3 data in eeprom.\n");
116 if (ddr3_default.version != settings.ddr3.version)
117 printf("Error: DDR3 data version does not match.\n");
118
119 printf("Using default settings\n");
120 set_default_ddr3_timings();
121 }
122
123 if (MAGIC_CHIP == settings.chip.magic) {
124 printf("Valid chip data in eeprom\n");
125 print_chip_data();
126 } else {
127 printf("Error: No chip data in eeprom\n");
128 }
129
130 print_ddr3_timings();
131#endif
132 return 0;
133}
134
135#ifdef CONFIG_SPL_BUILD
136static void board_init_ddr(void)
137{
138struct emif_regs dxr2_ddr3_emif_reg_data = {
139 .zq_config = 0x50074BE4,
140};
141
142struct ddr_data dxr2_ddr3_data = {
143};
144
145struct cmd_control dxr2_ddr3_cmd_ctrl_data = {
146};
147
148struct ctrl_ioregs dxr2_ddr3_ioregs = {
149};
150
151
152 dxr2_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1;
153 dxr2_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2;
154 dxr2_ddr3_emif_reg_data.sdram_tim3 = settings.ddr3.sdram_tim3;
155 dxr2_ddr3_emif_reg_data.emif_ddr_phy_ctlr_1 =
156 settings.ddr3.emif_ddr_phy_ctlr_1;
157 dxr2_ddr3_emif_reg_data.sdram_config = settings.ddr3.sdram_config;
158 dxr2_ddr3_emif_reg_data.ref_ctrl = settings.ddr3.ref_ctrl;
159
160 dxr2_ddr3_data.datardsratio0 = settings.ddr3.dt0rdsratio0;
161 dxr2_ddr3_data.datawdsratio0 = settings.ddr3.dt0wdsratio0;
162 dxr2_ddr3_data.datafwsratio0 = settings.ddr3.dt0fwsratio0;
163 dxr2_ddr3_data.datawrsratio0 = settings.ddr3.dt0wrsratio0;
164
165 dxr2_ddr3_cmd_ctrl_data.cmd0csratio = settings.ddr3.ddr3_sratio;
166 dxr2_ddr3_cmd_ctrl_data.cmd0iclkout = settings.ddr3.iclkout;
167 dxr2_ddr3_cmd_ctrl_data.cmd1csratio = settings.ddr3.ddr3_sratio;
168 dxr2_ddr3_cmd_ctrl_data.cmd1iclkout = settings.ddr3.iclkout;
169 dxr2_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio;
170 dxr2_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout;
171
172 dxr2_ddr3_ioregs.cm0ioctl = settings.ddr3.ioctr_val,
173 dxr2_ddr3_ioregs.cm1ioctl = settings.ddr3.ioctr_val,
174 dxr2_ddr3_ioregs.cm2ioctl = settings.ddr3.ioctr_val,
175 dxr2_ddr3_ioregs.dt0ioctl = settings.ddr3.ioctr_val,
176 dxr2_ddr3_ioregs.dt1ioctl = settings.ddr3.ioctr_val,
177
178 config_ddr(DDR_PLL_FREQ, &dxr2_ddr3_ioregs, &dxr2_ddr3_data,
179 &dxr2_ddr3_cmd_ctrl_data, &dxr2_ddr3_emif_reg_data, 0);
180}
181
182static void spl_siemens_board_init(void)
183{
184 return;
185}
186#endif
187
188#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
189 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
190static void cpsw_control(int enabled)
191{
192
193
194 return;
195}
196
197static struct cpsw_slave_data cpsw_slaves[] = {
198 {
199 .slave_reg_ofs = 0x208,
200 .sliver_reg_ofs = 0xd80,
201 .phy_id = 0,
202 .phy_if = PHY_INTERFACE_MODE_MII,
203 },
204};
205
206static struct cpsw_platform_data cpsw_data = {
207 .mdio_base = CPSW_MDIO_BASE,
208 .cpsw_base = CPSW_BASE,
209 .mdio_div = 0xff,
210 .channels = 4,
211 .cpdma_reg_ofs = 0x800,
212 .slaves = 1,
213 .slave_data = cpsw_slaves,
214 .ale_reg_ofs = 0xd00,
215 .ale_entries = 1024,
216 .host_port_reg_ofs = 0x108,
217 .hw_stats_reg_ofs = 0x900,
218 .bd_ram_ofs = 0x2000,
219 .mac_control = (1 << 5),
220 .control = cpsw_control,
221 .host_port_num = 0,
222 .version = CPSW_CTRL_VERSION_2,
223};
224
225#if defined(CONFIG_DRIVER_TI_CPSW) || \
226 (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
227int board_eth_init(bd_t *bis)
228{
229 struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
230 int n = 0;
231 int rv;
232
233 factoryset_setenv();
234
235
236 writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);
237
238 rv = cpsw_register(&cpsw_data);
239 if (rv < 0)
240 printf("Error %d registering CPSW switch\n", rv);
241 else
242 n += rv;
243 return n;
244}
245#endif
246#endif
247
248#include "../common/board.c"
249
