LXR uboot/board/spd8xx/spd8xx.c

   1/*
   2 * (C) Copyright 2000
   3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4 * Ulrich Lutz, Speech Design GmbH, ulutz@datalab.de.
   5 *
   6 * SPDX-License-Identifier:     GPL-2.0+
   7 */
   8
   9#include <common.h>
  10#include <mpc8xx.h>
  11#include <commproc.h>
  12
  13/* ------------------------------------------------------------------------- */
  14
  15static long int dram_size (long int, long int *, long int);
  16
  17/* ------------------------------------------------------------------------- */
  18
  19#define _NOT_USED_      0xFFFFFFFF
  20
  21const uint sharc_table[] = {
  22        /*
  23         * Single Read. (Offset 0 in UPM RAM)
  24         */
  25        0x0FF3FC04, 0x0FF3EC00, 0x7FFFEC04, 0xFFFFEC04,
  26        0xFFFFEC05,             /* last */
  27        _NOT_USED_, _NOT_USED_, _NOT_USED_,
  28        /*
  29         * Burst Read. (Offset 8 in UPM RAM)
  30         */
  31        /* last */
  32        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  33        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  34        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  35        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  36        /*
  37         * Single Write. (Offset 18 in UPM RAM)
  38         */
  39        0x0FAFFC04, 0x0FAFEC00, 0x7FFFEC04, 0xFFFFEC04,
  40        0xFFFFEC05,             /* last */
  41        _NOT_USED_, _NOT_USED_, _NOT_USED_,
  42        /*
  43         * Burst Write. (Offset 20 in UPM RAM)
  44         */
  45        /* last */
  46        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  47        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  48        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  49        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  50        /*
  51         * Refresh  (Offset 30 in UPM RAM)
  52         */
  53        /* last */
  54        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  55        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  56        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  57        /*
  58         * Exception. (Offset 3c in UPM RAM)
  59         */
  60        0x7FFFFC07,             /* last */
  61        _NOT_USED_, _NOT_USED_, _NOT_USED_,
  62};
  63
  64
  65const uint sdram_table[] = {
  66        /*
  67         * Single Read. (Offset 0 in UPM RAM)
  68         */
  69        0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
  70        0x1FF77C47,             /* last */
  71        /*
  72         * SDRAM Initialization (offset 5 in UPM RAM)
  73         *
  74         * This is no UPM entry point. The following definition uses
  75         * the remaining space to establish an initialization
  76         * sequence, which is executed by a RUN command.
  77         *
  78         */
  79        0x1FF77C35, 0xEFEABC34, 0x1FB57C35,     /* last */
  80        /*
  81         * Burst Read. (Offset 8 in UPM RAM)
  82         */
  83        0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
  84        0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
  85        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  86        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  87        /*
  88         * Single Write. (Offset 18 in UPM RAM)
  89         */
  90        0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
  91        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  92        /*
  93         * Burst Write. (Offset 20 in UPM RAM)
  94         */
  95        0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
  96        0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47,     /* last */
  97        _NOT_USED_,
  98        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  99        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 100        /*
 101         * Refresh  (Offset 30 in UPM RAM)
 102         */
 103        0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
 104        0xFFFFFC84, 0xFFFFFC07, /* last */
 105        _NOT_USED_, _NOT_USED_,
 106        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 107        /*
 108         * Exception. (Offset 3c in UPM RAM)
 109         */
 110        0x7FFFFC07,             /* last */
 111        _NOT_USED_, _NOT_USED_, _NOT_USED_,
 112};
 113
 114/* ------------------------------------------------------------------------- */
 115
 116
 117/*
 118 * Check Board Identity:
 119 *
 120 */
 121
 122int checkboard (void)
 123{
 124        puts ("Board: SPD823TS\n");
 125        return (0);
 126}
 127
 128/* ------------------------------------------------------------------------- */
 129
 130phys_size_t initdram (int board_type)
 131{
 132        volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 133        volatile memctl8xx_t *memctl = &immap->im_memctl;
 134        long int size_b0;
 135
 136#if 0
 137        /*
 138         * Map controller bank 2 to the SRAM bank at preliminary address.
 139         */
 140        memctl->memc_or2 = CONFIG_SYS_OR2;
 141        memctl->memc_br2 = CONFIG_SYS_BR2;
 142#endif
 143
 144        /*
 145         * Map controller bank 4 to the PER8 bank.
 146         */
 147        memctl->memc_or4 = CONFIG_SYS_OR4;
 148        memctl->memc_br4 = CONFIG_SYS_BR4;
 149
 150#if 0
 151        /* Configure SHARC at UMA */
 152        upmconfig (UPMA, (uint *) sharc_table,
 153                   sizeof (sharc_table) / sizeof (uint));
 154        /* Map controller bank 5 to the SHARC */
 155        memctl->memc_or5 = CONFIG_SYS_OR5;
 156        memctl->memc_br5 = CONFIG_SYS_BR5;
 157#endif
 158
 159        memctl->memc_mamr = 0x00001000;
 160
 161        /* Configure SDRAM at UMB */
 162        upmconfig (UPMB, (uint *) sdram_table,
 163                   sizeof (sdram_table) / sizeof (uint));
 164
 165        memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_8K;
 166
 167        memctl->memc_mar = 0x00000088;
 168
 169        /*
 170         * Map controller bank 3 to the SDRAM bank at preliminary address.
 171         */
 172        memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
 173        memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
 174
 175        memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL;       /* refresh not enabled yet */
 176
 177        udelay (200);
 178        memctl->memc_mcr = 0x80806105;
 179        udelay (1);
 180        memctl->memc_mcr = 0x80806130;
 181        udelay (1);
 182        memctl->memc_mcr = 0x80806130;
 183        udelay (1);
 184        memctl->memc_mcr = 0x80806106;
 185
 186        memctl->memc_mbmr |= MBMR_PTBE; /* refresh enabled */
 187
 188        /*
 189         * Check Bank 0 Memory Size for re-configuration
 190         */
 191        size_b0 =
 192                dram_size (CONFIG_SYS_MBMR_8COL, SDRAM_BASE3_PRELIM,
 193                           SDRAM_MAX_SIZE);
 194
 195        memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL | MBMR_PTBE;
 196
 197        return (size_b0);
 198}
 199
 200/* ------------------------------------------------------------------------- */
 201
 202/*
 203 * Check memory range for valid RAM. A simple memory test determines
 204 * the actually available RAM size between addresses `base' and
 205 * `base + maxsize'. Some (not all) hardware errors are detected:
 206 * - short between address lines
 207 * - short between data lines
 208 */
 209
 210static long int dram_size (long int mamr_value, long int *base,
 211                           long int maxsize)
 212{
 213        volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 214        volatile memctl8xx_t *memctl = &immap->im_memctl;
 215
 216        memctl->memc_mbmr = mamr_value;
 217
 218        return (get_ram_size (base, maxsize));
 219}
 220
 221/* ------------------------------------------------------------------------- */
 222
 223void reset_phy (void)
 224{
 225        immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 226        ushort sreg;
 227
 228        /* Configure extra port pins for NS DP83843 PHY */
 229        immr->im_ioport.iop_papar &= ~(PA_ENET_MDC | PA_ENET_MDIO);
 230
 231        sreg = immr->im_ioport.iop_padir;
 232        sreg |= PA_ENET_MDC;    /* Mgmt. Data Clock is Output */
 233        sreg &= ~(PA_ENET_MDIO);        /* Mgmt. Data I/O is bidirect. => Input */
 234        immr->im_ioport.iop_padir = sreg;
 235
 236        immr->im_ioport.iop_padat &= ~(PA_ENET_MDC);    /* set MDC = 0 */
 237
 238        /*
 239         * RESET in implemented by a positive pulse of at least 1 us
 240         * at the reset pin.
 241         *
 242         * Configure RESET pins for NS DP83843 PHY, and RESET chip.
 243         *
 244         * Note: The RESET pin is high active, but there is an
 245         *       inverter on the SPD823TS board...
 246         */
 247        immr->im_ioport.iop_pcpar &= ~(PC_ENET_RESET);
 248        immr->im_ioport.iop_pcdir |= PC_ENET_RESET;
 249        /* assert RESET signal of PHY */
 250        immr->im_ioport.iop_pcdat &= ~(PC_ENET_RESET);
 251        udelay (10);
 252        /* de-assert RESET signal of PHY */
 253        immr->im_ioport.iop_pcdat |= PC_ENET_RESET;
 254        udelay (10);
 255}
 256
 257/* ------------------------------------------------------------------------- */
 258
 259void ide_set_reset (int on)
 260{
 261        volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 262
 263        /*
 264         * Configure PC for IDE Reset Pin
 265         */
 266        if (on) {               /* assert RESET */
 267                immr->im_ioport.iop_pcdat &= ~(CONFIG_SYS_PC_IDE_RESET);
 268        } else {                /* release RESET */
 269                immr->im_ioport.iop_pcdat |= CONFIG_SYS_PC_IDE_RESET;
 270        }
 271
 272        /* program port pin as GPIO output */
 273        immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_IDE_RESET);
 274        immr->im_ioport.iop_pcso &= ~(CONFIG_SYS_PC_IDE_RESET);
 275        immr->im_ioport.iop_pcdir |= CONFIG_SYS_PC_IDE_RESET;
 276}
 277
 278/* ------------------------------------------------------------------------- */
 279