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16#include <common.h>
17#include <command.h>
18#include <asm/processor.h>
19#include <asm/io.h>
20#include <pci.h>
21
22
23
24
25
26void pci_header_show(pci_dev_t dev);
27void pci_header_show_brief(pci_dev_t dev);
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40
41void pciinfo(int BusNum, int ShortPCIListing)
42{
43 int Device;
44 int Function;
45 unsigned char HeaderType;
46 unsigned short VendorID;
47 pci_dev_t dev;
48
49 printf("Scanning PCI devices on bus %d\n", BusNum);
50
51 if (ShortPCIListing) {
52 printf("BusDevFun VendorId DeviceId Device Class Sub-Class\n");
53 printf("_____________________________________________________________\n");
54 }
55
56 for (Device = 0; Device < PCI_MAX_PCI_DEVICES; Device++) {
57 HeaderType = 0;
58 VendorID = 0;
59 for (Function = 0; Function < PCI_MAX_PCI_FUNCTIONS; Function++) {
60
61
62
63 if (Function && !(HeaderType & 0x80))
64 break;
65
66 dev = PCI_BDF(BusNum, Device, Function);
67
68 pci_read_config_word(dev, PCI_VENDOR_ID, &VendorID);
69 if ((VendorID == 0xFFFF) || (VendorID == 0x0000))
70 continue;
71
72 if (!Function) pci_read_config_byte(dev, PCI_HEADER_TYPE, &HeaderType);
73
74 if (ShortPCIListing)
75 {
76 printf("%02x.%02x.%02x ", BusNum, Device, Function);
77 pci_header_show_brief(dev);
78 }
79 else
80 {
81 printf("\nFound PCI device %02x.%02x.%02x:\n",
82 BusNum, Device, Function);
83 pci_header_show(dev);
84 }
85 }
86 }
87}
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100
101void pci_header_show_brief(pci_dev_t dev)
102{
103 u16 vendor, device;
104 u8 class, subclass;
105
106 pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
107 pci_read_config_word(dev, PCI_DEVICE_ID, &device);
108 pci_read_config_byte(dev, PCI_CLASS_CODE, &class);
109 pci_read_config_byte(dev, PCI_CLASS_SUB_CODE, &subclass);
110
111 printf("0x%.4x 0x%.4x %-23s 0x%.2x\n",
112 vendor, device,
113 pci_class_str(class), subclass);
114}
115
116
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118
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120
121
122
123
124
125
126void pci_header_show(pci_dev_t dev)
127{
128 u8 _byte, header_type;
129 u16 _word;
130 u32 _dword;
131
132#define PRINT(msg, type, reg) \
133 pci_read_config_##type(dev, reg, &_##type); \
134 printf(msg, _##type)
135
136#define PRINT2(msg, type, reg, func) \
137 pci_read_config_##type(dev, reg, &_##type); \
138 printf(msg, _##type, func(_##type))
139
140 pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);
141
142 PRINT (" vendor ID = 0x%.4x\n", word, PCI_VENDOR_ID);
143 PRINT (" device ID = 0x%.4x\n", word, PCI_DEVICE_ID);
144 PRINT (" command register = 0x%.4x\n", word, PCI_COMMAND);
145 PRINT (" status register = 0x%.4x\n", word, PCI_STATUS);
146 PRINT (" revision ID = 0x%.2x\n", byte, PCI_REVISION_ID);
147 PRINT2(" class code = 0x%.2x (%s)\n", byte, PCI_CLASS_CODE,
148 pci_class_str);
149 PRINT (" sub class code = 0x%.2x\n", byte, PCI_CLASS_SUB_CODE);
150 PRINT (" programming interface = 0x%.2x\n", byte, PCI_CLASS_PROG);
151 PRINT (" cache line = 0x%.2x\n", byte, PCI_CACHE_LINE_SIZE);
152 PRINT (" latency time = 0x%.2x\n", byte, PCI_LATENCY_TIMER);
153 PRINT (" header type = 0x%.2x\n", byte, PCI_HEADER_TYPE);
154 PRINT (" BIST = 0x%.2x\n", byte, PCI_BIST);
155 PRINT (" base address 0 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_0);
156
157 switch (header_type & 0x03) {
158 case PCI_HEADER_TYPE_NORMAL:
159 PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
160 PRINT (" base address 2 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_2);
161 PRINT (" base address 3 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_3);
162 PRINT (" base address 4 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_4);
163 PRINT (" base address 5 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_5);
164 PRINT (" cardBus CIS pointer = 0x%.8x\n", dword, PCI_CARDBUS_CIS);
165 PRINT (" sub system vendor ID = 0x%.4x\n", word, PCI_SUBSYSTEM_VENDOR_ID);
166 PRINT (" sub system ID = 0x%.4x\n", word, PCI_SUBSYSTEM_ID);
167 PRINT (" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS);
168 PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
169 PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
170 PRINT (" min Grant = 0x%.2x\n", byte, PCI_MIN_GNT);
171 PRINT (" max Latency = 0x%.2x\n", byte, PCI_MAX_LAT);
172 break;
173
174 case PCI_HEADER_TYPE_BRIDGE:
175
176 PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
177 PRINT (" primary bus number = 0x%.2x\n", byte, PCI_PRIMARY_BUS);
178 PRINT (" secondary bus number = 0x%.2x\n", byte, PCI_SECONDARY_BUS);
179 PRINT (" subordinate bus number = 0x%.2x\n", byte, PCI_SUBORDINATE_BUS);
180 PRINT (" secondary latency timer = 0x%.2x\n", byte, PCI_SEC_LATENCY_TIMER);
181 PRINT (" IO base = 0x%.2x\n", byte, PCI_IO_BASE);
182 PRINT (" IO limit = 0x%.2x\n", byte, PCI_IO_LIMIT);
183 PRINT (" secondary status = 0x%.4x\n", word, PCI_SEC_STATUS);
184 PRINT (" memory base = 0x%.4x\n", word, PCI_MEMORY_BASE);
185 PRINT (" memory limit = 0x%.4x\n", word, PCI_MEMORY_LIMIT);
186 PRINT (" prefetch memory base = 0x%.4x\n", word, PCI_PREF_MEMORY_BASE);
187 PRINT (" prefetch memory limit = 0x%.4x\n", word, PCI_PREF_MEMORY_LIMIT);
188 PRINT (" prefetch memory base upper = 0x%.8x\n", dword, PCI_PREF_BASE_UPPER32);
189 PRINT (" prefetch memory limit upper = 0x%.8x\n", dword, PCI_PREF_LIMIT_UPPER32);
190 PRINT (" IO base upper 16 bits = 0x%.4x\n", word, PCI_IO_BASE_UPPER16);
191 PRINT (" IO limit upper 16 bits = 0x%.4x\n", word, PCI_IO_LIMIT_UPPER16);
192 PRINT (" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS1);
193 PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
194 PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
195 PRINT (" bridge control = 0x%.4x\n", word, PCI_BRIDGE_CONTROL);
196 break;
197
198 case PCI_HEADER_TYPE_CARDBUS:
199
200 PRINT (" capabilities = 0x%.2x\n", byte, PCI_CB_CAPABILITY_LIST);
201 PRINT (" secondary status = 0x%.4x\n", word, PCI_CB_SEC_STATUS);
202 PRINT (" primary bus number = 0x%.2x\n", byte, PCI_CB_PRIMARY_BUS);
203 PRINT (" CardBus number = 0x%.2x\n", byte, PCI_CB_CARD_BUS);
204 PRINT (" subordinate bus number = 0x%.2x\n", byte, PCI_CB_SUBORDINATE_BUS);
205 PRINT (" CardBus latency timer = 0x%.2x\n", byte, PCI_CB_LATENCY_TIMER);
206 PRINT (" CardBus memory base 0 = 0x%.8x\n", dword, PCI_CB_MEMORY_BASE_0);
207 PRINT (" CardBus memory limit 0 = 0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_0);
208 PRINT (" CardBus memory base 1 = 0x%.8x\n", dword, PCI_CB_MEMORY_BASE_1);
209 PRINT (" CardBus memory limit 1 = 0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_1);
210 PRINT (" CardBus IO base 0 = 0x%.4x\n", word, PCI_CB_IO_BASE_0);
211 PRINT (" CardBus IO base high 0 = 0x%.4x\n", word, PCI_CB_IO_BASE_0_HI);
212 PRINT (" CardBus IO limit 0 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_0);
213 PRINT (" CardBus IO limit high 0 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_0_HI);
214 PRINT (" CardBus IO base 1 = 0x%.4x\n", word, PCI_CB_IO_BASE_1);
215 PRINT (" CardBus IO base high 1 = 0x%.4x\n", word, PCI_CB_IO_BASE_1_HI);
216 PRINT (" CardBus IO limit 1 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_1);
217 PRINT (" CardBus IO limit high 1 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_1_HI);
218 PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
219 PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
220 PRINT (" bridge control = 0x%.4x\n", word, PCI_CB_BRIDGE_CONTROL);
221 PRINT (" subvendor ID = 0x%.4x\n", word, PCI_CB_SUBSYSTEM_VENDOR_ID);
222 PRINT (" subdevice ID = 0x%.4x\n", word, PCI_CB_SUBSYSTEM_ID);
223 PRINT (" PC Card 16bit base address = 0x%.8x\n", dword, PCI_CB_LEGACY_MODE_BASE);
224 break;
225
226 default:
227 printf("unknown header\n");
228 break;
229 }
230
231#undef PRINT
232#undef PRINT2
233}
234
235
236
237static pci_dev_t get_pci_dev(char* name)
238{
239 char cnum[12];
240 int len, i, iold, n;
241 int bdfs[3] = {0,0,0};
242
243 len = strlen(name);
244 if (len > 8)
245 return -1;
246 for (i = 0, iold = 0, n = 0; i < len; i++) {
247 if (name[i] == '.') {
248 memcpy(cnum, &name[iold], i - iold);
249 cnum[i - iold] = '\0';
250 bdfs[n++] = simple_strtoul(cnum, NULL, 16);
251 iold = i + 1;
252 }
253 }
254 strcpy(cnum, &name[iold]);
255 if (n == 0)
256 n = 1;
257 bdfs[n] = simple_strtoul(cnum, NULL, 16);
258 return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]);
259}
260
261static int pci_cfg_display(pci_dev_t bdf, ulong addr, ulong size, ulong length)
262{
263#define DISP_LINE_LEN 16
264 ulong i, nbytes, linebytes;
265 int rc = 0;
266
267 if (length == 0)
268 length = 0x40 / size;
269
270
271
272
273 nbytes = length * size;
274 do {
275 uint val4;
276 ushort val2;
277 u_char val1;
278
279 printf("%08lx:", addr);
280 linebytes = (nbytes>DISP_LINE_LEN)?DISP_LINE_LEN:nbytes;
281 for (i=0; i<linebytes; i+= size) {
282 if (size == 4) {
283 pci_read_config_dword(bdf, addr, &val4);
284 printf(" %08x", val4);
285 } else if (size == 2) {
286 pci_read_config_word(bdf, addr, &val2);
287 printf(" %04x", val2);
288 } else {
289 pci_read_config_byte(bdf, addr, &val1);
290 printf(" %02x", val1);
291 }
292 addr += size;
293 }
294 printf("\n");
295 nbytes -= linebytes;
296 if (ctrlc()) {
297 rc = 1;
298 break;
299 }
300 } while (nbytes > 0);
301
302 return (rc);
303}
304
305static int pci_cfg_write (pci_dev_t bdf, ulong addr, ulong size, ulong value)
306{
307 if (size == 4) {
308 pci_write_config_dword(bdf, addr, value);
309 }
310 else if (size == 2) {
311 ushort val = value & 0xffff;
312 pci_write_config_word(bdf, addr, val);
313 }
314 else {
315 u_char val = value & 0xff;
316 pci_write_config_byte(bdf, addr, val);
317 }
318 return 0;
319}
320
321static int
322pci_cfg_modify (pci_dev_t bdf, ulong addr, ulong size, ulong value, int incrflag)
323{
324 ulong i;
325 int nbytes;
326 uint val4;
327 ushort val2;
328 u_char val1;
329
330
331
332
333 do {
334 printf("%08lx:", addr);
335 if (size == 4) {
336 pci_read_config_dword(bdf, addr, &val4);
337 printf(" %08x", val4);
338 }
339 else if (size == 2) {
340 pci_read_config_word(bdf, addr, &val2);
341 printf(" %04x", val2);
342 }
343 else {
344 pci_read_config_byte(bdf, addr, &val1);
345 printf(" %02x", val1);
346 }
347
348 nbytes = readline (" ? ");
349 if (nbytes == 0 || (nbytes == 1 && console_buffer[0] == '-')) {
350
351
352
353 if (incrflag)
354 addr += nbytes ? -size : size;
355 nbytes = 1;
356#ifdef CONFIG_BOOT_RETRY_TIME
357 reset_cmd_timeout();
358#endif
359 }
360#ifdef CONFIG_BOOT_RETRY_TIME
361 else if (nbytes == -2) {
362 break;
363 }
364#endif
365 else {
366 char *endp;
367 i = simple_strtoul(console_buffer, &endp, 16);
368 nbytes = endp - console_buffer;
369 if (nbytes) {
370#ifdef CONFIG_BOOT_RETRY_TIME
371
372
373 reset_cmd_timeout();
374#endif
375 pci_cfg_write (bdf, addr, size, i);
376 if (incrflag)
377 addr += size;
378 }
379 }
380 } while (nbytes);
381
382 return 0;
383}
384
385
386
387
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389
390
391
392
393static int do_pci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
394{
395 ulong addr = 0, value = 0, size = 0;
396 pci_dev_t bdf = 0;
397 char cmd = 's';
398
399 if (argc > 1)
400 cmd = argv[1][0];
401
402 switch (cmd) {
403 case 'd':
404 case 'n':
405 case 'm':
406 case 'w':
407
408 size = cmd_get_data_size(argv[1], 4);
409 if (argc > 3)
410 addr = simple_strtoul(argv[3], NULL, 16);
411 if (argc > 4)
412 value = simple_strtoul(argv[4], NULL, 16);
413 case 'h':
414 if (argc < 3)
415 goto usage;
416 if ((bdf = get_pci_dev(argv[2])) == -1)
417 return 1;
418 break;
419#ifdef CONFIG_CMD_PCI_ENUM
420 case 'e':
421 break;
422#endif
423 default:
424 value = 1;
425 bdf = 0;
426 if (argc > 1) {
427 if (argv[argc-1][0] == 'l') {
428 value = 0;
429 argc--;
430 }
431 if (argc > 1)
432 bdf = simple_strtoul(argv[1], NULL, 16);
433 }
434 pciinfo(bdf, value);
435 return 0;
436 }
437
438 switch (argv[1][0]) {
439 case 'h':
440 pci_header_show(bdf);
441 return 0;
442 case 'd':
443 return pci_cfg_display(bdf, addr, size, value);
444#ifdef CONFIG_CMD_PCI_ENUM
445 case 'e':
446 pci_init();
447 return 0;
448#endif
449 case 'n':
450 if (argc < 4)
451 goto usage;
452 return pci_cfg_modify(bdf, addr, size, value, 0);
453 case 'm':
454 if (argc < 4)
455 goto usage;
456 return pci_cfg_modify(bdf, addr, size, value, 1);
457 case 'w':
458 if (argc < 5)
459 goto usage;
460 return pci_cfg_write(bdf, addr, size, value);
461 }
462
463 return 1;
464 usage:
465 return CMD_RET_USAGE;
466}
467
468
469
470#ifdef CONFIG_SYS_LONGHELP
471static char pci_help_text[] =
472 "[bus] [long]\n"
473 " - short or long list of PCI devices on bus 'bus'\n"
474#ifdef CONFIG_CMD_PCI_ENUM
475 "pci enum\n"
476 " - re-enumerate PCI buses\n"
477#endif
478 "pci header b.d.f\n"
479 " - show header of PCI device 'bus.device.function'\n"
480 "pci display[.b, .w, .l] b.d.f [address] [# of objects]\n"
481 " - display PCI configuration space (CFG)\n"
482 "pci next[.b, .w, .l] b.d.f address\n"
483 " - modify, read and keep CFG address\n"
484 "pci modify[.b, .w, .l] b.d.f address\n"
485 " - modify, auto increment CFG address\n"
486 "pci write[.b, .w, .l] b.d.f address value\n"
487 " - write to CFG address";
488#endif
489
490U_BOOT_CMD(
491 pci, 5, 1, do_pci,
492 "list and access PCI Configuration Space", pci_help_text
493);
494
