1/* 2 * (C) Copyright 2001-2005 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8/* 9 * 10 * Configuration settings for the CPC45 board. 11 * 12 */ 13 14/* ------------------------------------------------------------------------- */ 15 16/* 17 * board/config.h - configuration options, board specific 18 */ 19 20#ifndef __CONFIG_H 21#define __CONFIG_H 22 23/* 24 * High Level Configuration Options 25 * (easy to change) 26 */ 27 28#define CONFIG_MPC824X 1 29#define CONFIG_MPC8245 1 30#define CONFIG_CPC45 1 31 32#define CONFIG_SYS_TEXT_BASE 0xFFF00000 33 34#define CONFIG_CONS_INDEX 1 35#define CONFIG_BAUDRATE 9600 36 37#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" 38 39#define CONFIG_BOOTDELAY 5 40 41/* 42 * BOOTP options 43 */ 44#define CONFIG_BOOTP_SUBNETMASK 45#define CONFIG_BOOTP_GATEWAY 46#define CONFIG_BOOTP_HOSTNAME 47#define CONFIG_BOOTP_BOOTPATH 48 49#define CONFIG_BOOTP_BOOTFILESIZE 50 51 52/* 53 * Command line configuration. 54 */ 55#include <config_cmd_default.h> 56 57#define CONFIG_CMD_BEDBUG 58#define CONFIG_CMD_DATE 59#define CONFIG_CMD_DHCP 60#define CONFIG_CMD_EEPROM 61#define CONFIG_CMD_EXT2 62#define CONFIG_CMD_FAT 63#define CONFIG_CMD_FLASH 64#define CONFIG_CMD_I2C 65#define CONFIG_CMD_IDE 66#define CONFIG_CMD_NFS 67#define CONFIG_CMD_PCI 68#define CONFIG_CMD_PING 69#define CONFIG_CMD_SDRAM 70#define CONFIG_CMD_SNTP 71 72 73/* 74 * Miscellaneous configurable options 75 */ 76#define CONFIG_SYS_LONGHELP /* undef to save memory */ 77#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 78 79#if 1 80#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ 81#endif 82 83/* Print Buffer Size 84 */ 85#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 86 87#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 88#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 89#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */ 90 91/*----------------------------------------------------------------------- 92 * Start addresses for the final memory configuration 93 * (Set up by the startup code) 94 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 95 */ 96 97#define CONFIG_SYS_SDRAM_BASE 0x00000000 98 99#if defined(CONFIG_BOOT_ROM) 100#define CONFIG_SYS_FLASH_BASE 0xFF000000 101#else 102#define CONFIG_SYS_FLASH_BASE 0xFF800000 103#endif 104 105#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 106 107#define CONFIG_SYS_EUMB_ADDR 0xFCE00000 108 109#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 110 111#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 112#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 113 114#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */ 115#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ 116 117/* Maximum amount of RAM. 118 */ 119#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000 120 121 122#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE 123#undef CONFIG_SYS_RAMBOOT 124#else 125#define CONFIG_SYS_RAMBOOT 126#endif 127 128 129/*----------------------------------------------------------------------- 130 * Definitions for initial stack pointer and data area 131 */ 132 133#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 134#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 135#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 136 137/* 138 * NS16550 Configuration 139 */ 140#define CONFIG_SYS_NS16550 141#define CONFIG_SYS_NS16550_SERIAL 142 143#define CONFIG_SYS_NS16550_REG_SIZE 1 144 145#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 146 147#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_EUMB_ADDR + 0x4500) 148#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4600) 149#define DUART_DCR (CONFIG_SYS_EUMB_ADDR + 0x4511) 150 151/* 152 * I2C configuration 153 */ 154#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ 155 156#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ 157#define CONFIG_SYS_I2C_SLAVE 0x7F 158 159/* 160 * RTC configuration 161 */ 162#define CONFIG_RTC_PCF8563 163#define CONFIG_SYS_I2C_RTC_ADDR 0x51 164 165/* 166 * EEPROM configuration 167 */ 168#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 169#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 170#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 171#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 172#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 173 174/* 175 * Low Level Configuration Settings 176 * (address mappings, register initial values, etc.) 177 * You should know what you are doing if you make changes here. 178 * For the detail description refer to the MPC8240 user's manual. 179 */ 180 181#define CONFIG_SYS_CLK_FREQ 33000000 182 183 184/* Bit-field values for MCCR1. 185 */ 186#define CONFIG_SYS_ROMNAL 0 187#define CONFIG_SYS_ROMFAL 8 188 189#define CONFIG_SYS_BANK0_ROW 0 /* SDRAM bank 7-0 row address */ 190#define CONFIG_SYS_BANK1_ROW 0 191#define CONFIG_SYS_BANK2_ROW 0 192#define CONFIG_SYS_BANK3_ROW 0 193#define CONFIG_SYS_BANK4_ROW 0 194#define CONFIG_SYS_BANK5_ROW 0 195#define CONFIG_SYS_BANK6_ROW 0 196#define CONFIG_SYS_BANK7_ROW 0 197 198/* Bit-field values for MCCR2. 199 */ 200 201#define CONFIG_SYS_REFINT 0x2ec 202 203/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. 204 */ 205#define CONFIG_SYS_BSTOPRE 160 206 207/* Bit-field values for MCCR3. 208 */ 209#define CONFIG_SYS_REFREC 2 /* Refresh to activate interval */ 210#define CONFIG_SYS_RDLAT 0 /* Data latancy from read command */ 211 212/* Bit-field values for MCCR4. 213 */ 214#define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval */ 215#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */ 216#define CONFIG_SYS_SDMODE_CAS_LAT 2 /* SDMODE CAS latancy */ 217#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */ 218#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length */ 219#define CONFIG_SYS_ACTORW 2 220#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 221#define CONFIG_SYS_EXTROM 0 222#define CONFIG_SYS_REGDIMM 0 223 224/* Memory bank settings. 225 * Only bits 20-29 are actually used from these vales to set the 226 * start/end addresses. The upper two bits will always be 0, and the lower 227 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end 228 * address. Refer to the MPC8240 book. 229 */ 230 231#define CONFIG_SYS_BANK0_START 0x00000000 232#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1) 233#define CONFIG_SYS_BANK0_ENABLE 1 234#define CONFIG_SYS_BANK1_START 0x3ff00000 235#define CONFIG_SYS_BANK1_END 0x3fffffff 236#define CONFIG_SYS_BANK1_ENABLE 0 237#define CONFIG_SYS_BANK2_START 0x3ff00000 238#define CONFIG_SYS_BANK2_END 0x3fffffff 239#define CONFIG_SYS_BANK2_ENABLE 0 240#define CONFIG_SYS_BANK3_START 0x3ff00000 241#define CONFIG_SYS_BANK3_END 0x3fffffff 242#define CONFIG_SYS_BANK3_ENABLE 0 243#define CONFIG_SYS_BANK4_START 0x3ff00000 244#define CONFIG_SYS_BANK4_END 0x3fffffff 245#define CONFIG_SYS_BANK4_ENABLE 0 246#define CONFIG_SYS_BANK5_START 0x3ff00000 247#define CONFIG_SYS_BANK5_END 0x3fffffff 248#define CONFIG_SYS_BANK5_ENABLE 0 249#define CONFIG_SYS_BANK6_START 0x3ff00000 250#define CONFIG_SYS_BANK6_END 0x3fffffff 251#define CONFIG_SYS_BANK6_ENABLE 0 252#define CONFIG_SYS_BANK7_START 0x3ff00000 253#define CONFIG_SYS_BANK7_END 0x3fffffff 254#define CONFIG_SYS_BANK7_ENABLE 0 255 256#define CONFIG_SYS_ODCR 0xff 257#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */ 258 /* currently accessed page in memory */ 259 /* see 8240 book for details */ 260 261#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 262#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 263 264#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) 265#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 266 267#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) 268#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) 269 270#define CONFIG_SYS_IBAT3L (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT) 271#define CONFIG_SYS_IBAT3U (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP) 272 273#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 274#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 275#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 276#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 277#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 278#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 279#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 280#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 281 282/* 283 * For booting Linux, the board info and command line data 284 * have to be in the first 8 MB of memory, since this is 285 * the maximum mapped by the Linux kernel during initialization. 286 */ 287#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 288 289/*----------------------------------------------------------------------- 290 * FLASH organization 291 */ 292#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */ 293#define CONFIG_SYS_MAX_FLASH_SECT 39 /* Max number of sectors in one bank */ 294#define INTEL_ID_28F160F3T 0x88F388F3 /* 16M = 1M x 16 top boot sector */ 295#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 296#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 297 298 /* Warining: environment is not EMBEDDED in the ppcboot code. 299 * It's stored in flash separately. 300 */ 301#define CONFIG_ENV_IS_IN_FLASH 1 302 303#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x7F8000) 304#define CONFIG_ENV_SIZE 0x4000 /* Size of the Environment */ 305#define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */ 306#define CONFIG_ENV_SECT_SIZE 0x8000 /* Size of the Environment Sector */ 307 308/*----------------------------------------------------------------------- 309 * Cache Configuration 310 */ 311#define CONFIG_SYS_CACHELINE_SIZE 32 312#if defined(CONFIG_CMD_KGDB) 313# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 314#endif 315 316/*----------------------------------------------------------------------*/ 317/* CPC45 Memory Map */ 318/*----------------------------------------------------------------------*/ 319#define SRAM_BASE 0x80000000 /* SRAM base address */ 320#define SRAM_END 0x801FFFFF 321#define ST16552_A_BASE 0x80200000 /* ST16552 channel A */ 322#define ST16552_B_BASE 0x80400000 /* ST16552 channel A */ 323#define BCSR_BASE 0x80600000 /* board control / status registers */ 324#define DISPLAY_BASE 0x80600040 /* DISPLAY base */ 325#define PCMCIA_MEM_BASE 0x83000000 /* PCMCIA memory window base */ 326#define PCMCIA_IO_BASE 0xFE000000 /* PCMCIA IO window base */ 327 328#define CONFIG_SYS_SRAM_BASE SRAM_BASE 329#define CONFIG_SYS_SRAM_SIZE (SRAM_END - SRAM_BASE + 1) 330 331/*---------------------------------------------------------------------*/ 332/* CPC45 Control/Status Registers */ 333/*---------------------------------------------------------------------*/ 334#define IRQ_ENA_1 *((volatile uchar*)(BCSR_BASE + 0x00)) 335#define IRQ_STAT_1 *((volatile uchar*)(BCSR_BASE + 0x01)) 336#define IRQ_ENA_2 *((volatile uchar*)(BCSR_BASE + 0x02)) 337#define IRQ_STAT_2 *((volatile uchar*)(BCSR_BASE + 0x03)) 338#define BOARD_CTRL *((volatile uchar*)(BCSR_BASE + 0x04)) 339#define BOARD_STAT *((volatile uchar*)(BCSR_BASE + 0x05)) 340#define WDG_START *((volatile uchar*)(BCSR_BASE + 0x06)) 341#define WDG_PRESTOP *((volatile uchar*)(BCSR_BASE + 0x06)) 342#define WDG_STOP *((volatile uchar*)(BCSR_BASE + 0x06)) 343#define BOARD_REV *((volatile uchar*)(BCSR_BASE + 0x07)) 344 345/* IRQ_ENA_1 bit definitions */ 346#define I_ENA_1_IERA 0x80 /* INTA enable */ 347#define I_ENA_1_IERB 0x40 /* INTB enable */ 348#define I_ENA_1_IERC 0x20 /* INTC enable */ 349#define I_ENA_1_IERD 0x10 /* INTD enable */ 350 351/* IRQ_STAT_1 bit definitions */ 352#define I_STAT_1_INTA 0x80 /* INTA status */ 353#define I_STAT_1_INTB 0x40 /* INTB status */ 354#define I_STAT_1_INTC 0x20 /* INTC status */ 355#define I_STAT_1_INTD 0x10 /* INTD status */ 356 357/* IRQ_ENA_2 bit definitions */ 358#define I_ENA_2_IEAB 0x80 /* ABORT IRQ enable */ 359#define I_ENA_2_IEK1 0x40 /* KEY1 IRQ enable */ 360#define I_ENA_2_IEK2 0x20 /* KEY2 IRQ enable */ 361#define I_ENA_2_IERT 0x10 /* RTC IRQ enable */ 362#define I_ENA_2_IESM 0x08 /* LM81 IRQ enable */ 363#define I_ENA_2_IEDG 0x04 /* DEGENERATING IRQ enable */ 364#define I_ENA_2_IES2 0x02 /* ST16552/B IRQ enable */ 365#define I_ENA_2_IES1 0x01 /* ST16552/A IRQ enable */ 366 367/* IRQ_STAT_2 bit definitions */ 368#define I_STAT_2_ABO 0x80 /* ABORT IRQ status */ 369#define I_STAT_2_KY1 0x40 /* KEY1 IRQ status */ 370#define I_STAT_2_KY2 0x20 /* KEY2 IRQ status */ 371#define I_STAT_2_RTC 0x10 /* RTC IRQ status */ 372#define I_STAT_2_SMN 0x08 /* LM81 IRQ status */ 373#define I_STAT_2_DEG 0x04 /* DEGENERATING IRQ status */ 374#define I_STAT_2_SIO2 0x02 /* ST16552/B IRQ status */ 375#define I_STAT_2_SIO1 0x01 /* ST16552/A IRQ status */ 376 377/* BOARD_CTRL bit definitions */ 378#define USER_LEDS 2 /* 2 user LEDs */ 379 380#if (USER_LEDS == 4) 381#define B_CTRL_WRSE 0x80 382#define B_CTRL_KRSE 0x40 383#define B_CTRL_FWRE 0x20 /* Flash write enable */ 384#define B_CTRL_FWPT 0x10 /* Flash write protect */ 385#define B_CTRL_LED3 0x08 /* LED 3 control */ 386#define B_CTRL_LED2 0x04 /* LED 2 control */ 387#define B_CTRL_LED1 0x02 /* LED 1 control */ 388#define B_CTRL_LED0 0x01 /* LED 0 control */ 389#else 390#define B_CTRL_WRSE 0x80 391#define B_CTRL_KRSE 0x40 392#define B_CTRL_FWRE_1 0x20 /* Flash write enable */ 393#define B_CTRL_FWPT_1 0x10 /* Flash write protect */ 394#define B_CTRL_LED1 0x08 /* LED 1 control */ 395#define B_CTRL_LED0 0x04 /* LED 0 control */ 396#define B_CTRL_FWRE_0 0x02 /* Flash write enable */ 397#define B_CTRL_FWPT_0 0x01 /* Flash write protect */ 398#endif 399 400/* BOARD_STAT bit definitions */ 401#define B_STAT_WDGE 0x80 402#define B_STAT_WDGS 0x40 403#define B_STAT_WRST 0x20 404#define B_STAT_KRST 0x10 405#define B_STAT_CSW3 0x08 /* sitch bit 3 status */ 406#define B_STAT_CSW2 0x04 /* sitch bit 2 status */ 407#define B_STAT_CSW1 0x02 /* sitch bit 1 status */ 408#define B_STAT_CSW0 0x01 /* sitch bit 0 status */ 409 410/*---------------------------------------------------------------------*/ 411/* Display addresses */ 412/*---------------------------------------------------------------------*/ 413#define DISP_UDC_RAM (DISPLAY_BASE + 0x08) /* UDC RAM */ 414#define DISP_CHR_RAM (DISPLAY_BASE + 0x18) /* character Ram */ 415#define DISP_FLASH (DISPLAY_BASE + 0x20) /* Flash Ram */ 416 417#define DISP_UDC_ADR *((volatile uchar*)(DISPLAY_BASE + 0x00)) /* UDC Address Reg. */ 418#define DISP_CWORD *((volatile uchar*)(DISPLAY_BASE + 0x10)) /* Control Word Reg. */ 419 420#define DISP_DIG0 *((volatile uchar*)(DISP_CHR_RAM + 0x00)) /* Digit 0 address */ 421#define DISP_DIG1 *((volatile uchar*)(DISP_CHR_RAM + 0x01)) /* Digit 0 address */ 422#define DISP_DIG2 *((volatile uchar*)(DISP_CHR_RAM + 0x02)) /* Digit 0 address */ 423#define DISP_DIG3 *((volatile uchar*)(DISP_CHR_RAM + 0x03)) /* Digit 0 address */ 424#define DISP_DIG4 *((volatile uchar*)(DISP_CHR_RAM + 0x04)) /* Digit 0 address */ 425#define DISP_DIG5 *((volatile uchar*)(DISP_CHR_RAM + 0x05)) /* Digit 0 address */ 426#define DISP_DIG6 *((volatile uchar*)(DISP_CHR_RAM + 0x06)) /* Digit 0 address */ 427#define DISP_DIG7 *((volatile uchar*)(DISP_CHR_RAM + 0x07)) /* Digit 0 address */ 428 429 430/*----------------------------------------------------------------------- 431 * PCI stuff 432 *----------------------------------------------------------------------- 433 */ 434#define CONFIG_PCI /* include pci support */ 435#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 436#define CONFIG_SYS_EARLY_PCI_INIT 437#undef CONFIG_PCI_PNP 438#undef CONFIG_PCI_SCAN_SHOW 439 440 441#define CONFIG_EEPRO100 442#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ 443 444#define PCI_ENET0_IOADDR 0x82000000 445#define PCI_ENET0_MEMADDR 0x82000000 446#define PCI_PLX9030_IOADDR 0x82100000 447#define PCI_PLX9030_MEMADDR 0x82100000 448 449/*----------------------------------------------------------------------- 450 * PCMCIA stuff 451 *----------------------------------------------------------------------- 452 */ 453 454#define CONFIG_I82365 455 456#define CONFIG_SYS_PCMCIA_MEM_ADDR PCMCIA_MEM_BASE 457#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x1000 458 459#define CONFIG_PCMCIA_SLOT_A 460 461/*----------------------------------------------------------------------- 462 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) 463 *----------------------------------------------------------------------- 464 */ 465 466#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ 467#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ 468 469#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 470#undef CONFIG_IDE_RESET /* reset for IDE not supported */ 471#define CONFIG_IDE_LED /* LED for IDE is supported */ 472 473#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 474#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 475 476#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 477 478#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 479 480#define CONFIG_SYS_ATA_DATA_OFFSET CONFIG_SYS_PCMCIA_MEM_SIZE 481 482/* Offset for normal register accesses */ 483#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 484 485/* Offset for alternate registers */ 486#define CONFIG_SYS_ATA_ALT_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x400) 487 488#define CONFIG_DOS_PARTITION 489 490#endif /* __CONFIG_H */ 491