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8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
12#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
13#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
14#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
15#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
16#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
17
18#ifdef CONFIG_NAND_U_BOOT
19#define CONFIG_SYS_TEXT_BASE 0x00100000
20#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
21#ifdef CONFIG_NAND_SPL
22#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL
23#endif
24#endif
25
26#ifndef CONFIG_SYS_TEXT_BASE
27#define CONFIG_SYS_TEXT_BASE 0xFE000000
28#endif
29
30#ifndef CONFIG_SYS_MONITOR_BASE
31#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
32#endif
33
34
35
36
37#define CONFIG_E300 1
38#define CONFIG_MPC83xx 1
39#define CONFIG_MPC831x 1
40#define CONFIG_MPC8315 1
41#define CONFIG_MPC8315ERDB 1
42
43
44
45
46#define CONFIG_83XX_CLKIN 66666667
47#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
48
49
50
51
52
53
54#define CONFIG_SYS_HRCW_LOW (\
55 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
56 HRCWL_DDR_TO_SCB_CLK_2X1 |\
57 HRCWL_SVCOD_DIV_2 |\
58 HRCWL_CSB_TO_CLKIN_2X1 |\
59 HRCWL_CORE_TO_CSB_3X1)
60#define CONFIG_SYS_HRCW_HIGH_BASE (\
61 HRCWH_PCI_HOST |\
62 HRCWH_PCI1_ARBITER_ENABLE |\
63 HRCWH_CORE_ENABLE |\
64 HRCWH_BOOTSEQ_DISABLE |\
65 HRCWH_SW_WATCHDOG_DISABLE |\
66 HRCWH_TSEC1M_IN_RGMII |\
67 HRCWH_TSEC2M_IN_RGMII |\
68 HRCWH_BIG_ENDIAN |\
69 HRCWH_LALE_NORMAL)
70
71#ifdef CONFIG_NAND_SPL
72#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
73 HRCWH_FROM_0XFFF00100 |\
74 HRCWH_ROM_LOC_NAND_SP_8BIT |\
75 HRCWH_RL_EXT_NAND)
76#else
77#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
78 HRCWH_FROM_0X00000100 |\
79 HRCWH_ROM_LOC_LOCAL_16BIT |\
80 HRCWH_RL_EXT_LEGACY)
81#endif
82
83
84
85
86#define CONFIG_SYS_SICRH 0x00000000
87#define CONFIG_SYS_SICRL 0x00000000
88
89#define CONFIG_BOARD_EARLY_INIT_F
90#define CONFIG_HWCONFIG
91
92
93
94
95#define CONFIG_SYS_IMMR 0xE0000000
96
97#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
98#define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
99#endif
100
101
102
103
104#define CONFIG_SYS_ACR_PIPE_DEP 3
105#define CONFIG_SYS_ACR_RPTCNT 3
106#define CONFIG_SYS_SPCR_TSECEP 3
107
108
109
110
111#define CONFIG_SYS_DDR_BASE 0x00000000
112#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
113#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
114#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
115#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
116 | DDRCDR_PZ_LOZ \
117 | DDRCDR_NZ_LOZ \
118 | DDRCDR_ODT \
119 | DDRCDR_Q_DRN)
120
121
122
123
124
125#define CONFIG_SYS_DDR_SIZE 128
126#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
127#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
128 | CSCONFIG_ODT_RD_NEVER \
129 | CSCONFIG_ODT_WR_ONLY_CURRENT \
130 | CSCONFIG_ROW_BIT_13 \
131 | CSCONFIG_COL_BIT_10)
132
133#define CONFIG_SYS_DDR_TIMING_3 0x00000000
134#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
135 | (0 << TIMING_CFG0_WRT_SHIFT) \
136 | (0 << TIMING_CFG0_RRT_SHIFT) \
137 | (0 << TIMING_CFG0_WWT_SHIFT) \
138 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
139 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
140 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
141 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
142
143#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
144 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
145 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
146 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
147 | (6 << TIMING_CFG1_REFREC_SHIFT) \
148 | (2 << TIMING_CFG1_WRREC_SHIFT) \
149 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
150 | (2 << TIMING_CFG1_WRTORD_SHIFT))
151
152#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
153 | (4 << TIMING_CFG2_CPO_SHIFT) \
154 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
155 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
156 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
157 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
158 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
159
160#define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
161 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
162
163#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
164 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
165 | SDRAM_CFG_DBW_32)
166
167#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
168#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
169 | (0x0232 << SDRAM_MODE_SD_SHIFT))
170
171#define CONFIG_SYS_DDR_MODE2 0x00000000
172
173
174
175
176#undef CONFIG_SYS_DRAM_TEST
177#define CONFIG_SYS_MEMTEST_START 0x00040000
178#define CONFIG_SYS_MEMTEST_END 0x00140000
179
180
181
182
183#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
184#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
185
186
187
188
189#define CONFIG_SYS_INIT_RAM_LOCK 1
190#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000
191#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
192#define CONFIG_SYS_GBL_DATA_OFFSET \
193 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
194
195
196
197
198#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
199#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
200#define CONFIG_SYS_LBC_LBCR 0x00040000
201#define CONFIG_FSL_ELBC 1
202
203
204
205
206#define CONFIG_SYS_FLASH_CFI
207#define CONFIG_FLASH_CFI_DRIVER
208#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
209
210#define CONFIG_SYS_FLASH_BASE 0xFE000000
211#define CONFIG_SYS_FLASH_SIZE 8
212#define CONFIG_SYS_FLASH_PROTECTION 1
213
214
215#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
216#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
217
218#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \
219 | BR_PS_16 \
220 | BR_MS_GPCM \
221 | BR_V)
222#define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
223 | OR_UPM_XAM \
224 | OR_GPCM_CSNT \
225 | OR_GPCM_ACS_DIV2 \
226 | OR_GPCM_XACS \
227 | OR_GPCM_SCY_15 \
228 | OR_GPCM_TRLX_SET \
229 | OR_GPCM_EHTR_SET \
230 | OR_GPCM_EAD)
231
232#define CONFIG_SYS_MAX_FLASH_BANKS 1
233
234#define CONFIG_SYS_MAX_FLASH_SECT 135
235
236#undef CONFIG_SYS_FLASH_CHECKSUM
237#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
238#define CONFIG_SYS_FLASH_WRITE_TOUT 500
239
240
241
242
243
244#ifdef CONFIG_NAND_SPL
245#define CONFIG_SYS_NAND_BASE 0xFFF00000
246#else
247#define CONFIG_SYS_NAND_BASE 0xE0600000
248#endif
249
250#define CONFIG_MTD_DEVICE
251#define CONFIG_MTD_PARTITION
252#define CONFIG_CMD_MTDPARTS
253#define MTDIDS_DEFAULT "nand0=e0600000.flash"
254#define MTDPARTS_DEFAULT \
255 "mtdparts=e0600000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)"
256
257#define CONFIG_SYS_MAX_NAND_DEVICE 1
258#define CONFIG_MTD_NAND_VERIFY_WRITE 1
259#define CONFIG_CMD_NAND 1
260#define CONFIG_NAND_FSL_ELBC 1
261#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
262#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
263
264#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
265#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
266#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
267#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
268#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
269
270#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
271 | BR_DECC_CHK_GEN \
272 | BR_PS_8 \
273 | BR_MS_FCM \
274 | BR_V)
275#define CONFIG_SYS_NAND_OR_PRELIM \
276 (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
277 | OR_FCM_CSCT \
278 | OR_FCM_CST \
279 | OR_FCM_CHT \
280 | OR_FCM_SCY_1 \
281 | OR_FCM_TRLX \
282 | OR_FCM_EHTR)
283
284
285#ifdef CONFIG_NAND_U_BOOT
286#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
287#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
288#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM
289#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM
290#else
291#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
292#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
293#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
294#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
295#endif
296
297#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
298#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
299
300#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
301#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
302
303#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \
304 !defined(CONFIG_NAND_SPL)
305#define CONFIG_SYS_RAMBOOT
306#else
307#undef CONFIG_SYS_RAMBOOT
308#endif
309
310
311
312
313#define CONFIG_CONS_INDEX 1
314#define CONFIG_SYS_NS16550
315#define CONFIG_SYS_NS16550_SERIAL
316#define CONFIG_SYS_NS16550_REG_SIZE 1
317#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
318
319#define CONFIG_SYS_BAUDRATE_TABLE \
320 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
321
322#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
323#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
324
325
326#define CONFIG_SYS_HUSH_PARSER
327
328
329#define CONFIG_OF_LIBFDT 1
330#define CONFIG_OF_BOARD_SETUP 1
331#define CONFIG_OF_STDOUT_VIA_ALIAS 1
332
333
334#define CONFIG_SYS_I2C
335#define CONFIG_SYS_I2C_FSL
336#define CONFIG_SYS_FSL_I2C_SPEED 400000
337#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
338#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
339#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
340
341
342
343
344#define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39
345
346
347
348
349#define CONFIG_RTC_DS1337
350#define CONFIG_SYS_I2C_RTC_ADDR 0x68
351
352
353
354
355
356#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
357#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
358#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
359#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
360#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
361#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000
362#define CONFIG_SYS_PCI_IO_BASE 0x00000000
363#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
364#define CONFIG_SYS_PCI_IO_SIZE 0x100000
365
366#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
367#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
368#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
369
370#define CONFIG_SYS_PCIE1_BASE 0xA0000000
371#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
372#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
373#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
374#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
375#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
376#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
377#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
378#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
379
380#define CONFIG_SYS_PCIE2_BASE 0xC0000000
381#define CONFIG_SYS_PCIE2_MEM_BASE 0xC0000000
382#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC0000000
383#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
384#define CONFIG_SYS_PCIE2_CFG_BASE 0xD0000000
385#define CONFIG_SYS_PCIE2_CFG_SIZE 0x01000000
386#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
387#define CONFIG_SYS_PCIE2_IO_PHYS 0xD1000000
388#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
389
390#define CONFIG_PCI
391#define CONFIG_PCI_INDIRECT_BRIDGE
392#define CONFIG_PCIE
393
394#define CONFIG_PCI_PNP
395
396#define CONFIG_EEPRO100
397#undef CONFIG_PCI_SCAN_SHOW
398#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957
399
400#define CONFIG_HAS_FSL_DR_USB
401#define CONFIG_SYS_SCCR_USBDRCM 3
402
403#define CONFIG_CMD_USB
404#define CONFIG_USB_STORAGE
405#define CONFIG_USB_EHCI
406#define CONFIG_USB_EHCI_FSL
407#define CONFIG_USB_PHY_TYPE "utmi"
408#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
409
410
411
412
413#define CONFIG_TSEC_ENET
414#define CONFIG_SYS_TSEC1_OFFSET 0x24000
415#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
416#define CONFIG_SYS_TSEC2_OFFSET 0x25000
417#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
418
419
420
421
422#define CONFIG_MII 1
423#define CONFIG_TSEC1 1
424#define CONFIG_TSEC1_NAME "eTSEC0"
425#define CONFIG_TSEC2 1
426#define CONFIG_TSEC2_NAME "eTSEC1"
427#define TSEC1_PHY_ADDR 0
428#define TSEC2_PHY_ADDR 1
429#define TSEC1_PHYIDX 0
430#define TSEC2_PHYIDX 0
431#define TSEC1_FLAGS TSEC_GIGABIT
432#define TSEC2_FLAGS TSEC_GIGABIT
433
434
435#define CONFIG_ETHPRIME "eTSEC1"
436
437
438
439
440#define CONFIG_LIBATA
441#define CONFIG_FSL_SATA
442
443#define CONFIG_SYS_SATA_MAX_DEVICE 2
444#define CONFIG_SATA1
445#define CONFIG_SYS_SATA1_OFFSET 0x18000
446#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
447#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
448#define CONFIG_SATA2
449#define CONFIG_SYS_SATA2_OFFSET 0x19000
450#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
451#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
452
453#ifdef CONFIG_FSL_SATA
454#define CONFIG_LBA48
455#define CONFIG_CMD_SATA
456#define CONFIG_DOS_PARTITION
457#define CONFIG_CMD_EXT2
458#endif
459
460
461
462
463#if defined(CONFIG_NAND_U_BOOT)
464 #define CONFIG_ENV_IS_IN_NAND 1
465 #define CONFIG_ENV_OFFSET (512 * 1024)
466 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
467 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
468 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
469 #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4)
470 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
471 CONFIG_ENV_RANGE)
472#elif !defined(CONFIG_SYS_RAMBOOT)
473 #define CONFIG_ENV_IS_IN_FLASH 1
474 #define CONFIG_ENV_ADDR \
475 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
476 #define CONFIG_ENV_SECT_SIZE 0x10000
477 #define CONFIG_ENV_SIZE 0x2000
478#else
479 #define CONFIG_SYS_NO_FLASH 1
480 #define CONFIG_ENV_IS_NOWHERE 1
481 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
482 #define CONFIG_ENV_SIZE 0x2000
483#endif
484
485#define CONFIG_LOADS_ECHO 1
486#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
487
488
489
490
491#define CONFIG_BOOTP_BOOTFILESIZE
492#define CONFIG_BOOTP_BOOTPATH
493#define CONFIG_BOOTP_GATEWAY
494#define CONFIG_BOOTP_HOSTNAME
495
496
497
498
499#include <config_cmd_default.h>
500
501#define CONFIG_CMD_PING
502#define CONFIG_CMD_I2C
503#define CONFIG_CMD_MII
504#define CONFIG_CMD_DATE
505#define CONFIG_CMD_PCI
506
507#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
508 #undef CONFIG_CMD_SAVEENV
509 #undef CONFIG_CMD_LOADS
510#endif
511
512#define CONFIG_CMDLINE_EDITING 1
513#define CONFIG_AUTO_COMPLETE
514
515#undef CONFIG_WATCHDOG
516
517
518
519
520#define CONFIG_SYS_LONGHELP
521#define CONFIG_SYS_LOAD_ADDR 0x2000000
522
523#if defined(CONFIG_CMD_KGDB)
524 #define CONFIG_SYS_CBSIZE 1024
525#else
526 #define CONFIG_SYS_CBSIZE 256
527#endif
528
529
530#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
531#define CONFIG_SYS_MAXARGS 16
532
533#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
534
535
536
537
538
539
540#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
541
542
543
544
545#define CONFIG_SYS_HID0_INIT 0x000000000
546#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
547 HID0_ENABLE_INSTRUCTION_CACHE | \
548 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
549#define CONFIG_SYS_HID2 HID2_HBE
550
551
552
553
554#define CONFIG_HIGH_BATS 1
555
556
557#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
558 | BATL_PP_RW \
559 | BATL_MEMCOHERENCE)
560#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
561 | BATU_BL_128M \
562 | BATU_VS \
563 | BATU_VP)
564#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
565#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
566
567
568#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
569 | BATL_PP_RW \
570 | BATL_CACHEINHIBIT \
571 | BATL_GUARDEDSTORAGE)
572#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
573 | BATU_BL_8M \
574 | BATU_VS \
575 | BATU_VP)
576#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
577#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
578
579
580#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \
581 | BATL_PP_RW \
582 | BATL_MEMCOHERENCE)
583#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \
584 | BATU_BL_32M \
585 | BATU_VS \
586 | BATU_VP)
587#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \
588 | BATL_PP_RW \
589 | BATL_CACHEINHIBIT \
590 | BATL_GUARDEDSTORAGE)
591#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
592
593
594#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
595#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR \
596 | BATU_BL_128K \
597 | BATU_VS \
598 | BATU_VP)
599#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
600#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
601
602
603#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI_MEM_PHYS \
604 | BATL_PP_RW \
605 | BATL_MEMCOHERENCE)
606#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI_MEM_PHYS \
607 | BATU_BL_256M \
608 | BATU_VS \
609 | BATU_VP)
610#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
611#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
612
613
614#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI_MMIO_PHYS \
615 | BATL_PP_RW \
616 | BATL_CACHEINHIBIT \
617 | BATL_GUARDEDSTORAGE)
618#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI_MMIO_PHYS \
619 | BATU_BL_256M \
620 | BATU_VS \
621 | BATU_VP)
622#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
623#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
624
625#define CONFIG_SYS_IBAT6L 0
626#define CONFIG_SYS_IBAT6U 0
627#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
628#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
629
630#define CONFIG_SYS_IBAT7L 0
631#define CONFIG_SYS_IBAT7U 0
632#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
633#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
634
635#if defined(CONFIG_CMD_KGDB)
636#define CONFIG_KGDB_BAUDRATE 230400
637#endif
638
639
640
641
642
643#define CONFIG_ENV_OVERWRITE
644
645#if defined(CONFIG_TSEC_ENET)
646#define CONFIG_HAS_ETH0
647#define CONFIG_HAS_ETH1
648#endif
649
650#define CONFIG_BAUDRATE 115200
651
652#define CONFIG_LOADADDR 800000
653
654#define CONFIG_BOOTDELAY 6
655#undef CONFIG_BOOTARGS
656
657#define CONFIG_EXTRA_ENV_SETTINGS \
658 "netdev=eth0\0" \
659 "consoledev=ttyS0\0" \
660 "ramdiskaddr=1000000\0" \
661 "ramdiskfile=ramfs.83xx\0" \
662 "fdtaddr=780000\0" \
663 "fdtfile=mpc8315erdb.dtb\0" \
664 "usb_phy_type=utmi\0" \
665 ""
666
667#define CONFIG_NFSBOOTCOMMAND \
668 "setenv bootargs root=/dev/nfs rw " \
669 "nfsroot=$serverip:$rootpath " \
670 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
671 "$netdev:off " \
672 "console=$consoledev,$baudrate $othbootargs;" \
673 "tftp $loadaddr $bootfile;" \
674 "tftp $fdtaddr $fdtfile;" \
675 "bootm $loadaddr - $fdtaddr"
676
677#define CONFIG_RAMBOOTCOMMAND \
678 "setenv bootargs root=/dev/ram rw " \
679 "console=$consoledev,$baudrate $othbootargs;" \
680 "tftp $ramdiskaddr $ramdiskfile;" \
681 "tftp $loadaddr $bootfile;" \
682 "tftp $fdtaddr $fdtfile;" \
683 "bootm $loadaddr $ramdiskaddr $fdtaddr"
684
685
686#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
687
688#endif
689