1/* 2 * (C) Copyright 2001 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8/* 9 * 10 * Configuration settings for the MUSENKI board. 11 * 12 */ 13 14/* ------------------------------------------------------------------------- */ 15 16/* 17 * board/config.h - configuration options, board specific 18 */ 19 20#ifndef __CONFIG_H 21#define __CONFIG_H 22 23/* 24 * High Level Configuration Options 25 * (easy to change) 26 */ 27 28#define CONFIG_MPC824X 1 29#define CONFIG_MPC8245 1 30#define CONFIG_MUSENKI 1 31 32#define CONFIG_SYS_TEXT_BASE 0xFFF00000 33 34#define CONFIG_CONS_INDEX 1 35#define CONFIG_BAUDRATE 9600 36 37#define CONFIG_BOOTDELAY 5 38 39 40/* 41 * BOOTP options 42 */ 43#define CONFIG_BOOTP_BOOTFILESIZE 44#define CONFIG_BOOTP_BOOTPATH 45#define CONFIG_BOOTP_GATEWAY 46#define CONFIG_BOOTP_HOSTNAME 47 48 49/* 50 * Command line configuration. 51 */ 52#include <config_cmd_default.h> 53 54 55/* 56 * Miscellaneous configurable options 57 */ 58#undef CONFIG_SYS_LONGHELP /* undef to save memory */ 59#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 60 61/* Print Buffer Size 62 */ 63#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 64#define CONFIG_SYS_MAXARGS 8 /* Max number of command args */ 65#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 66#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */ 67 68/*----------------------------------------------------------------------- 69 * PCI stuff 70 *----------------------------------------------------------------------- 71 */ 72#define CONFIG_PCI /* include pci support */ 73#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 74#undef CONFIG_PCI_PNP 75 76 77#define CONFIG_TULIP 78 79#define PCI_ENET0_IOADDR 0x80000000 80#define PCI_ENET0_MEMADDR 0x80000000 81#define PCI_ENET1_IOADDR 0x81000000 82#define PCI_ENET1_MEMADDR 0x81000000 83 84 85/*----------------------------------------------------------------------- 86 * Start addresses for the final memory configuration 87 * (Set up by the startup code) 88 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 89 */ 90#define CONFIG_SYS_SDRAM_BASE 0x00000000 91 92#define CONFIG_SYS_FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank on RCS#0 */ 93#define CONFIG_SYS_FLASH_BASE1_PRELIM 0xFF000000 /* FLASH bank on RCS#1 */ 94#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH_BASE0_PRELIM 95 96/* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the 97 * reset vector is actually located at FFB00100, but the 8245 98 * takes care of us. 99 */ 100#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 101 102#define CONFIG_SYS_EUMB_ADDR 0xFC000000 103 104#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 105#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 106#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 107 108#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */ 109#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ 110 111 /* Maximum amount of RAM. 112 */ 113#define CONFIG_SYS_MAX_RAM_SIZE 0x08000000 /* 0 .. 128 MB of (S)DRAM */ 114 115 116#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE 117#undef CONFIG_SYS_RAMBOOT 118#else 119#define CONFIG_SYS_RAMBOOT 120#endif 121 122/* 123 * NS16550 Configuration 124 */ 125#define CONFIG_SYS_NS16550 126#define CONFIG_SYS_NS16550_SERIAL 127 128#define CONFIG_SYS_NS16550_REG_SIZE 1 129 130#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 131 132#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_EUMB_ADDR + 0x4500) 133#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4600) 134 135/*----------------------------------------------------------------------- 136 * Definitions for initial stack pointer and data area 137 */ 138 139/* #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE */ 140#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 141#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 142#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 143 144 145/* 146 * Low Level Configuration Settings 147 * (address mappings, register initial values, etc.) 148 * You should know what you are doing if you make changes here. 149 * For the detail description refer to the MPC8240 user's manual. 150 */ 151 152#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ 153 154 /* Bit-field values for MCCR1. 155 */ 156#define CONFIG_SYS_ROMNAL 7 157#define CONFIG_SYS_ROMFAL 11 158#define CONFIG_SYS_DBUS_SIZE 0x3 159 160 /* Bit-field values for MCCR2. 161 */ 162#define CONFIG_SYS_TSWAIT 0x5 /* Transaction Start Wait States timer */ 163#define CONFIG_SYS_REFINT 0x400 /* Refresh interval FIXME: was 0t430 */ 164 165 /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. 166 */ 167#define CONFIG_SYS_BSTOPRE 121 168 169 /* Bit-field values for MCCR3. 170 */ 171#define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */ 172 173 /* Bit-field values for MCCR4. 174 */ 175#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval FIXME: was 2 */ 176#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval FIXME: was 5 */ 177#define CONFIG_SYS_ACTORW 3 /* FIXME was 2 */ 178#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */ 179#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */ 180#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 181#define CONFIG_SYS_EXTROM 1 182#define CONFIG_SYS_REGDIMM 0 183 184#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/ 185 186#define CONFIG_SYS_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */ 187 188/* Memory bank settings. 189 * Only bits 20-29 are actually used from these vales to set the 190 * start/end addresses. The upper two bits will always be 0, and the lower 191 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end 192 * address. Refer to the MPC8240 book. 193 */ 194 195#define CONFIG_SYS_BANK0_START 0x00000000 196#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1) 197#define CONFIG_SYS_BANK0_ENABLE 1 198#define CONFIG_SYS_BANK1_START 0x3ff00000 199#define CONFIG_SYS_BANK1_END 0x3fffffff 200#define CONFIG_SYS_BANK1_ENABLE 0 201#define CONFIG_SYS_BANK2_START 0x3ff00000 202#define CONFIG_SYS_BANK2_END 0x3fffffff 203#define CONFIG_SYS_BANK2_ENABLE 0 204#define CONFIG_SYS_BANK3_START 0x3ff00000 205#define CONFIG_SYS_BANK3_END 0x3fffffff 206#define CONFIG_SYS_BANK3_ENABLE 0 207#define CONFIG_SYS_BANK4_START 0x3ff00000 208#define CONFIG_SYS_BANK4_END 0x3fffffff 209#define CONFIG_SYS_BANK4_ENABLE 0 210#define CONFIG_SYS_BANK5_START 0x3ff00000 211#define CONFIG_SYS_BANK5_END 0x3fffffff 212#define CONFIG_SYS_BANK5_ENABLE 0 213#define CONFIG_SYS_BANK6_START 0x3ff00000 214#define CONFIG_SYS_BANK6_END 0x3fffffff 215#define CONFIG_SYS_BANK6_ENABLE 0 216#define CONFIG_SYS_BANK7_START 0x3ff00000 217#define CONFIG_SYS_BANK7_END 0x3fffffff 218#define CONFIG_SYS_BANK7_ENABLE 0 219 220#define CONFIG_SYS_ODCR 0xff 221 222#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 223#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 224 225#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) 226#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 227 228#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) 229#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) 230 231#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) 232#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 233 234#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 235#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 236#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 237#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 238#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 239#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 240#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 241#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 242 243/* 244 * For booting Linux, the board info and command line data 245 * have to be in the first 8 MB of memory, since this is 246 * the maximum mapped by the Linux kernel during initialization. 247 */ 248#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 249 250/*----------------------------------------------------------------------- 251 * FLASH organization 252 */ 253#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* Max number of flash banks */ 254#define CONFIG_SYS_MAX_FLASH_SECT 64 /* Max number of sectors per flash */ 255 256#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 257#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 258 259 260 /* Warining: environment is not EMBEDDED in the U-Boot code. 261 * It's stored in flash separately. 262 */ 263#define CONFIG_ENV_IS_IN_FLASH 1 264#define CONFIG_ENV_ADDR 0xFFFF0000 265#define CONFIG_ENV_SIZE 0x00010000 /* Size of the Environment */ 266#define CONFIG_ENV_SECT_SIZE 0x20000 /* Size of the Environment Sector */ 267 268/*----------------------------------------------------------------------- 269 * Cache Configuration 270 */ 271#define CONFIG_SYS_CACHELINE_SIZE 32 272#if defined(CONFIG_CMD_KGDB) 273# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 274#endif 275 276#endif /* __CONFIG_H */ 277