1/* 2 * Copyright (C) 2005-2006 Atmel Corporation 3 * 4 * Configuration settings for the ATSTK1002 CPU daughterboard 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8#ifndef __CONFIG_H 9#define __CONFIG_H 10 11#include <asm/arch/hardware.h> 12 13#define CONFIG_AVR32 14#define CONFIG_AT32AP 15#define CONFIG_AT32AP7000 16#define CONFIG_ATSTK1002 17#define CONFIG_ATSTK1000 18 19/* 20 * Set up the PLL to run at 140 MHz, the CPU to run at the PLL 21 * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the 22 * PLL frequency. 23 * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz 24 */ 25#define CONFIG_PLL 26#define CONFIG_SYS_POWER_MANAGER 27#define CONFIG_SYS_OSC0_HZ 20000000 28#define CONFIG_SYS_PLL0_DIV 1 29#define CONFIG_SYS_PLL0_MUL 7 30#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16 31/* 32 * Set the CPU running at: 33 * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz 34 */ 35#define CONFIG_SYS_CLKDIV_CPU 0 36/* 37 * Set the HSB running at: 38 * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz 39 */ 40#define CONFIG_SYS_CLKDIV_HSB 1 41/* 42 * Set the PBA running at: 43 * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz 44 */ 45#define CONFIG_SYS_CLKDIV_PBA 2 46/* 47 * Set the PBB running at: 48 * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz 49 */ 50#define CONFIG_SYS_CLKDIV_PBB 1 51 52/* Reserve VM regions for SDRAM and NOR flash */ 53#define CONFIG_SYS_NR_VM_REGIONS 2 54 55/* 56 * The PLLOPT register controls the PLL like this: 57 * icp = PLLOPT<2> 58 * ivco = PLLOPT<1:0> 59 * 60 * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). 61 */ 62#define CONFIG_SYS_PLL0_OPT 0x04 63 64#define CONFIG_USART_BASE ATMEL_BASE_USART1 65#define CONFIG_USART_ID 1 66 67/* User serviceable stuff */ 68#define CONFIG_DOS_PARTITION 69 70#define CONFIG_CMDLINE_TAG 71#define CONFIG_SETUP_MEMORY_TAGS 72#define CONFIG_INITRD_TAG 73 74#define CONFIG_STACKSIZE (2048) 75 76#define CONFIG_BAUDRATE 115200 77#define CONFIG_BOOTARGS \ 78 "console=ttyS0 root=/dev/mmcblk0p1 fbmem=600k rootwait=1" 79 80#define CONFIG_BOOTCOMMAND \ 81 "fsload; bootm $(fileaddr)" 82 83/* 84 * Only interrupt autoboot if <space> is pressed. Otherwise, garbage 85 * data on the serial line may interrupt the boot sequence. 86 */ 87#define CONFIG_BOOTDELAY 1 88#define CONFIG_AUTOBOOT 89#define CONFIG_AUTOBOOT_KEYED 90#define CONFIG_AUTOBOOT_PROMPT \ 91 "Press SPACE to abort autoboot in %d seconds\n", bootdelay 92#define CONFIG_AUTOBOOT_DELAY_STR "d" 93#define CONFIG_AUTOBOOT_STOP_STR " " 94 95/* 96 * After booting the board for the first time, new ethernet addresses 97 * should be generated and assigned to the environment variables 98 * "ethaddr" and "eth1addr". This is normally done during production. 99 */ 100#define CONFIG_OVERWRITE_ETHADDR_ONCE 101 102/* 103 * BOOTP options 104 */ 105#define CONFIG_BOOTP_SUBNETMASK 106#define CONFIG_BOOTP_GATEWAY 107 108 109/* 110 * Command line configuration. 111 */ 112#include <config_cmd_default.h> 113 114#define CONFIG_CMD_ASKENV 115#define CONFIG_CMD_DHCP 116#define CONFIG_CMD_EXT2 117#define CONFIG_CMD_FAT 118#define CONFIG_CMD_JFFS2 119#define CONFIG_CMD_MMC 120 121#undef CONFIG_CMD_FPGA 122#undef CONFIG_CMD_SETGETDCR 123#undef CONFIG_CMD_SOURCE 124#undef CONFIG_CMD_XIMG 125 126#define CONFIG_ATMEL_USART 127#define CONFIG_MACB 128#define CONFIG_PORTMUX_PIO 129#define CONFIG_SYS_NR_PIOS 5 130#define CONFIG_SYS_HSDRAMC 131#define CONFIG_MMC 132#define CONFIG_GENERIC_ATMEL_MCI 133#define CONFIG_GENERIC_MMC 134 135#define CONFIG_SYS_DCACHE_LINESZ 32 136#define CONFIG_SYS_ICACHE_LINESZ 32 137 138#define CONFIG_NR_DRAM_BANKS 1 139 140#define CONFIG_SYS_FLASH_CFI 141#define CONFIG_FLASH_CFI_DRIVER 142 143#define CONFIG_SYS_FLASH_BASE 0x00000000 144#define CONFIG_SYS_FLASH_SIZE 0x800000 145#define CONFIG_SYS_MAX_FLASH_BANKS 1 146#define CONFIG_SYS_MAX_FLASH_SECT 135 147 148#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 149#define CONFIG_SYS_TEXT_BASE 0x00000000 150 151#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE 152#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE 153#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE 154 155#define CONFIG_ENV_IS_IN_FLASH 156#define CONFIG_ENV_SIZE 65536 157#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE) 158 159#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE) 160 161#define CONFIG_SYS_MALLOC_LEN (256*1024) 162#define CONFIG_SYS_DMA_ALLOC_LEN (16384) 163 164/* Allow 4MB for the kernel run-time image */ 165#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) 166#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024) 167 168/* Other configuration settings that shouldn't have to change all that often */ 169#define CONFIG_SYS_PROMPT "U-Boot> " 170#define CONFIG_SYS_CBSIZE 256 171#define CONFIG_SYS_MAXARGS 16 172#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 173#define CONFIG_SYS_LONGHELP 174 175#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE 176#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x700000) 177#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } 178 179#endif /* __CONFIG_H */ 180