1/* 2 * (C) Copyright 2004 3 * Texas Instruments. 4 * Richard Woodruff <r-woodruff2@ti.com> 5 * Kshitij Gupta <kshitij@ti.com> 6 * 7 * Configuration settings for the LogicPD i.MX31 Litekit board. 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12#ifndef __CONFIG_H 13#define __CONFIG_H 14 15#include <asm/arch/imx-regs.h> 16 17 /* High Level Configuration Options */ 18#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ 19#define CONFIG_MX31 1 /* in a mx31 */ 20#define CONFIG_MX31_CLK32 32000 21 22#define CONFIG_DISPLAY_CPUINFO 23#define CONFIG_DISPLAY_BOARDINFO 24 25#define CONFIG_SYS_TEXT_BASE 0xa0000000 26 27#define CONFIG_MACH_TYPE MACH_TYPE_MX31LITE 28 29/* Temporarily disabled */ 30#if 0 31#define CONFIG_OF_LIBFDT 1 32#define CONFIG_FIT 1 33#define CONFIG_FIT_VERBOSE 1 34#endif 35 36#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 37#define CONFIG_SETUP_MEMORY_TAGS 1 38#define CONFIG_INITRD_TAG 1 39 40/* 41 * Size of malloc() pool 42 */ 43#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) 44 45/* 46 * Hardware drivers 47 */ 48 49#define CONFIG_MXC_UART 50#define CONFIG_MXC_UART_BASE UART1_BASE 51#define CONFIG_MXC_GPIO 52 53#define CONFIG_HARD_SPI 1 54#define CONFIG_MXC_SPI 1 55#define CONFIG_DEFAULT_SPI_BUS 1 56#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) 57 58/* PMIC Controller */ 59#define CONFIG_POWER 60#define CONFIG_POWER_SPI 61#define CONFIG_POWER_FSL 62#define CONFIG_FSL_PMIC_BUS 1 63#define CONFIG_FSL_PMIC_CS 0 64#define CONFIG_FSL_PMIC_CLK 1000000 65#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) 66#define CONFIG_FSL_PMIC_BITLEN 32 67#define CONFIG_RTC_MC13XXX 68 69/* allow to overwrite serial and ethaddr */ 70#define CONFIG_ENV_OVERWRITE 71#define CONFIG_CONS_INDEX 1 72#define CONFIG_BAUDRATE 115200 73 74/*********************************************************** 75 * Command definition 76 ***********************************************************/ 77 78#include <config_cmd_default.h> 79 80#define CONFIG_CMD_MII 81#define CONFIG_CMD_PING 82#define CONFIG_CMD_SPI 83#define CONFIG_CMD_DATE 84#define CONFIG_CMD_NAND 85 86#define CONFIG_BOOTDELAY 3 87 88#define CONFIG_NETMASK 255.255.255.0 89#define CONFIG_IPADDR 192.168.23.168 90#define CONFIG_SERVERIP 192.168.23.2 91 92#define CONFIG_EXTRA_ENV_SETTINGS \ 93 "bootargs_base=setenv bootargs console=ttySMX0,115200\0" \ 94 "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \ 95 "bootcmd=run bootcmd_net\0" \ 96 "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; tftpboot 0x80000000 uImage-mx31; bootm\0" \ 97 "prg_uboot=tftpboot 0x80000000 u-boot-imx31_litekit.bin; protect off all; erase 0xa00d0000 0xa01effff; cp.b 0x80000000 0xa00d0000 $(filesize)\0" 98 99 100#define CONFIG_SMC911X 1 101#define CONFIG_SMC911X_BASE (CS4_BASE + 0x00020000) 102#define CONFIG_SMC911X_32_BIT 1 103 104/* 105 * Miscellaneous configurable options 106 */ 107#define CONFIG_SYS_LONGHELP /* undef to save memory */ 108#define CONFIG_SYS_PROMPT "uboot> " 109#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 110/* Print Buffer Size */ 111#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 112#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 113#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 114 115#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ 116#define CONFIG_SYS_MEMTEST_END 0x10000 117 118#define CONFIG_SYS_LOAD_ADDR 0 /* default load address */ 119 120#define CONFIG_CMDLINE_EDITING 1 121 122/*----------------------------------------------------------------------- 123 * Physical Memory Map 124 */ 125#define CONFIG_NR_DRAM_BANKS 1 126#define PHYS_SDRAM_1 CSD0_BASE 127#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) 128#define CONFIG_BOARD_EARLY_INIT_F 129 130#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 131#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 132#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 133#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 134#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET) 135 136/*----------------------------------------------------------------------- 137 * FLASH and environment organization 138 */ 139#define CONFIG_SYS_FLASH_BASE CS0_BASE 140#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 141#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ 142#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */ 143 144#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x001f0000) 145#define CONFIG_ENV_IS_IN_FLASH 1 146#define CONFIG_ENV_SECT_SIZE (64 * 1024) 147#define CONFIG_ENV_SIZE (64 * 1024) 148 149/*----------------------------------------------------------------------- 150 * CFI FLASH driver setup 151 */ 152#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */ 153#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ 154#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ 155#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */ 156 157/* timeout values are in ticks */ 158#define CONFIG_SYS_FLASH_ERASE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ 159#define CONFIG_SYS_FLASH_WRITE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Write */ 160 161/* 162 * JFFS2 partitions 163 */ 164#undef CONFIG_CMD_MTDPARTS 165#define CONFIG_JFFS2_DEV "nor0" 166 167/* 168 * NAND flash 169 */ 170#define CONFIG_NAND_MXC 171#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR 172#define CONFIG_SYS_MAX_NAND_DEVICE 1 173#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR 174#define CONFIG_MXC_NAND_HWECC 175 176#endif /* __CONFIG_H */ 177