1/* 2 * Copyright (C) 2012 Keymile AG 3 * Gerlando Falauto <gerlando.falauto@keymile.com> 4 * 5 * Based on km8321-common.h, see respective copyright notice for credits 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10#ifndef __CONFIG_KM8309_COMMON_H 11#define __CONFIG_KM8309_COMMON_H 12 13/* 14 * High Level Configuration Options 15 */ 16#define CONFIG_E300 1 /* E300 family */ 17#define CONFIG_QE 1 /* Has QE */ 18#define CONFIG_MPC83xx 1 /* MPC83xx family */ 19#define CONFIG_MPC830x 1 /* MPC830x family */ 20#define CONFIG_MPC8309 1 /* MPC8309 CPU specific */ 21 22#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" 23#define CONFIG_CMD_DIAG 1 24 25/* include common defines/options for all 83xx Keymile boards */ 26#include "km83xx-common.h" 27 28/* QE microcode/firmware address */ 29#define CONFIG_SYS_QE_FMAN_FW_IN_NOR 30/* at end of uboot partition, before env */ 31#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xF00B0000 32 33/* 34 * System IO Config 35 */ 36/* 0x14000180 SICR_1 */ 37#define CONFIG_SYS_SICRL (0 \ 38 | SICR_1_UART1_UART1RTS \ 39 | SICR_1_I2C_CKSTOP \ 40 | SICR_1_IRQ_A_IRQ \ 41 | SICR_1_IRQ_B_IRQ \ 42 | SICR_1_GPIO_A_GPIO \ 43 | SICR_1_GPIO_B_GPIO \ 44 | SICR_1_GPIO_C_GPIO \ 45 | SICR_1_GPIO_D_GPIO \ 46 | SICR_1_GPIO_E_GPIO \ 47 | SICR_1_GPIO_F_GPIO \ 48 | SICR_1_USB_A_UART2S \ 49 | SICR_1_USB_B_UART2RTS \ 50 | SICR_1_FEC1_FEC1 \ 51 | SICR_1_FEC2_FEC2 \ 52 ) 53 54/* 0x00080400 SICR_2 */ 55#define CONFIG_SYS_SICRH (0 \ 56 | SICR_2_FEC3_FEC3 \ 57 | SICR_2_HDLC1_A_HDLC1 \ 58 | SICR_2_ELBC_A_LA \ 59 | SICR_2_ELBC_B_LCLK \ 60 | SICR_2_HDLC2_A_HDLC2 \ 61 | SICR_2_USB_D_GPIO \ 62 | SICR_2_PCI_PCI \ 63 | SICR_2_HDLC1_B_HDLC1 \ 64 | SICR_2_HDLC1_C_HDLC1 \ 65 | SICR_2_HDLC2_B_GPIO \ 66 | SICR_2_HDLC2_C_HDLC2 \ 67 | SICR_2_QUIESCE_B \ 68 ) 69 70/* GPR_1 */ 71#define CONFIG_SYS_GPR1 0x50008060 72 73#define CONFIG_SYS_GP1DIR 0x00000000 74#define CONFIG_SYS_GP1ODR 0x00000000 75#define CONFIG_SYS_GP2DIR 0xFF000000 76#define CONFIG_SYS_GP2ODR 0x00000000 77 78/* 79 * Hardware Reset Configuration Word 80 */ 81#define CONFIG_SYS_HRCW_LOW (\ 82 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ 83 HRCWL_DDR_TO_SCB_CLK_2X1 | \ 84 HRCWL_CSB_TO_CLKIN_2X1 | \ 85 HRCWL_CORE_TO_CSB_2X1 | \ 86 HRCWL_CE_PLL_VCO_DIV_2 | \ 87 HRCWL_CE_TO_PLL_1X3) 88 89#define CONFIG_SYS_HRCW_HIGH (\ 90 HRCWH_PCI_AGENT | \ 91 HRCWH_PCI_ARBITER_DISABLE | \ 92 HRCWH_CORE_ENABLE | \ 93 HRCWH_FROM_0X00000100 | \ 94 HRCWH_BOOTSEQ_DISABLE | \ 95 HRCWH_SW_WATCHDOG_DISABLE | \ 96 HRCWH_ROM_LOC_LOCAL_16BIT | \ 97 HRCWH_BIG_ENDIAN | \ 98 HRCWH_LALE_NORMAL) 99 100#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f 101#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ 102 SDRAM_CFG_32_BE | \ 103 SDRAM_CFG_SREN | \ 104 SDRAM_CFG_HSE) 105 106#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 107#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) 108#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ 109 (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) 110 111#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ 112 CSCONFIG_ODT_RD_NEVER | \ 113 CSCONFIG_ODT_WR_ONLY_CURRENT | \ 114 CSCONFIG_ROW_BIT_13 | \ 115 CSCONFIG_COL_BIT_10) 116 117#define CONFIG_SYS_DDR_MODE 0x47860242 118#define CONFIG_SYS_DDR_MODE2 0x8080c000 119 120#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ 121 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ 122 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ 123 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ 124 (0 << TIMING_CFG0_WWT_SHIFT) | \ 125 (0 << TIMING_CFG0_RRT_SHIFT) | \ 126 (0 << TIMING_CFG0_WRT_SHIFT) | \ 127 (0 << TIMING_CFG0_RWT_SHIFT)) 128 129#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ 130 (2 << TIMING_CFG1_WRTORD_SHIFT) | \ 131 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ 132 (3 << TIMING_CFG1_WRREC_SHIFT) | \ 133 (7 << TIMING_CFG1_REFREC_SHIFT) | \ 134 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ 135 (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ 136 (3 << TIMING_CFG1_PRETOACT_SHIFT)) 137 138#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ 139 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ 140 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ 141 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ 142 (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ 143 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ 144 (5 << TIMING_CFG2_CPO_SHIFT)) 145 146#define CONFIG_SYS_DDR_TIMING_3 0x00000000 147 148#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 149#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 150 151/* EEprom support */ 152#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 153 154/* 155 * Local Bus Configuration & Clock Setup 156 */ 157#define CONFIG_SYS_LCRR_DBYP 0x80000000 158#define CONFIG_SYS_LCRR_EADC 0x00010000 159#define CONFIG_SYS_LCRR_CLKDIV 0x00000002 160 161#define CONFIG_SYS_LBC_LBCR 0x00000000 162 163/* 164 * MMU Setup 165 */ 166#define CONFIG_SYS_IBAT7L (0) 167#define CONFIG_SYS_IBAT7U (0) 168#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 169#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 170 171#endif /* __CONFIG_KM8309_COMMON_H */ 172