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18#ifndef __CONFIG_H
19#define __CONFIG_H
20
21
22
23
24#ifdef CONFIG_CADDY2
25#define VME_CADDY2
26#endif
27
28
29
30
31#define CONFIG_E300 1
32#define CONFIG_MPC83xx 1
33#define CONFIG_MPC834x 1
34#define CONFIG_MPC8349 1
35#define CONFIG_VME8349 1
36
37#define CONFIG_SYS_TEXT_BASE 0xFFF00000
38
39#define CONFIG_MISC_INIT_R
40
41#define CONFIG_PCI
42
43#undef CONFIG_MPC83XX_PCI2
44
45#define CONFIG_PCI_66M
46#ifdef CONFIG_PCI_66M
47#define CONFIG_83XX_CLKIN 66000000
48#else
49#define CONFIG_83XX_CLKIN 33000000
50#endif
51
52#ifndef CONFIG_SYS_CLK_FREQ
53#ifdef CONFIG_PCI_66M
54#define CONFIG_SYS_CLK_FREQ 66000000
55#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
56#else
57#define CONFIG_SYS_CLK_FREQ 33000000
58#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
59#endif
60#endif
61
62#define CONFIG_SYS_IMMR 0xE0000000
63
64#undef CONFIG_SYS_DRAM_TEST
65#define CONFIG_SYS_MEMTEST_START 0x00000000
66#define CONFIG_SYS_MEMTEST_END 0x00100000
67
68
69
70
71#define CONFIG_DDR_ECC
72#define CONFIG_DDR_ECC_CMD
73#define CONFIG_SPD_EEPROM
74#define SPD_EEPROM_ADDRESS 0x54
75#define CONFIG_SYS_READ_SPD vme8349_read_spd
76#define CONFIG_SYS_83XX_DDR_USES_CS0
77
78
79
80
81
82
83
84
85
86
87
88#undef CONFIG_DDR_32BIT
89
90#define CONFIG_SYS_DDR_BASE 0x00000000
91#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
92#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
93#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
94 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
95#define CONFIG_DDR_2T_TIMING
96#define CONFIG_SYS_DDRCDR (DDRCDR_DHC_EN \
97 | DDRCDR_ODT \
98 | DDRCDR_Q_DRN)
99
100
101
102
103
104#define CONFIG_SYS_FLASH_CFI
105#define CONFIG_FLASH_CFI_DRIVER
106#ifdef VME_CADDY2
107#define CONFIG_SYS_FLASH_BASE 0xffc00000
108#define CONFIG_SYS_FLASH_SIZE 4
109#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
110 BR_PS_16 | \
111 BR_MS_GPCM | \
112 BR_V)
113
114#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
115 | OR_GPCM_XAM \
116 | OR_GPCM_CSNT \
117 | OR_GPCM_ACS_DIV2 \
118 | OR_GPCM_XACS \
119 | OR_GPCM_SCY_15 \
120 | OR_GPCM_TRLX_SET \
121 | OR_GPCM_EHTR_SET \
122 | OR_GPCM_EAD)
123
124#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
125#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_4MB)
126#else
127#define CONFIG_SYS_FLASH_BASE 0xf8000000
128#define CONFIG_SYS_FLASH_SIZE 128
129#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
130 BR_PS_16 | \
131 BR_MS_GPCM | \
132 BR_V)
133
134#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
135 | OR_GPCM_XAM \
136 | OR_GPCM_CSNT \
137 | OR_GPCM_ACS_DIV2 \
138 | OR_GPCM_XACS \
139 | OR_GPCM_SCY_15 \
140 | OR_GPCM_TRLX_SET \
141 | OR_GPCM_EHTR_SET \
142 | OR_GPCM_EAD)
143
144#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
145#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_128MB)
146#endif
147
148
149#define CONFIG_SYS_WINDOW1_BASE 0xf0000000
150#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_WINDOW1_BASE \
151 | BR_PS_32 \
152 | BR_MS_GPCM \
153 | BR_V)
154
155#define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB \
156 | OR_GPCM_SETA)
157
158#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_WINDOW1_BASE
159#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_256KB)
160
161#define CONFIG_SYS_MAX_FLASH_BANKS 1
162#define CONFIG_SYS_MAX_FLASH_SECT 1024
163
164#undef CONFIG_SYS_FLASH_CHECKSUM
165#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
166#define CONFIG_SYS_FLASH_WRITE_TOUT 500
167
168#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
169
170#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
171#define CONFIG_SYS_RAMBOOT
172#else
173#undef CONFIG_SYS_RAMBOOT
174#endif
175
176#define CONFIG_SYS_INIT_RAM_LOCK 1
177#define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000
178#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
179
180#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
181 GENERATED_GBL_DATA_SIZE)
182#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
183
184#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
185#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
186
187
188
189
190
191
192
193#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
194#define CONFIG_SYS_LBC_LBCR 0x00000000
195
196#undef CONFIG_SYS_LB_SDRAM
197
198
199
200
201#define CONFIG_CONS_INDEX 1
202#define CONFIG_SYS_NS16550
203#define CONFIG_SYS_NS16550_SERIAL
204#define CONFIG_SYS_NS16550_REG_SIZE 1
205#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
206
207#define CONFIG_SYS_BAUDRATE_TABLE \
208 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
209
210#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
211#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
212
213#define CONFIG_CMDLINE_EDITING
214#define CONFIG_AUTO_COMPLETE
215
216#define CONFIG_SYS_HUSH_PARSER
217
218
219#define CONFIG_OF_LIBFDT
220#define CONFIG_OF_BOARD_SETUP
221#define CONFIG_OF_STDOUT_VIA_ALIAS
222
223
224#define CONFIG_SYS_I2C
225#define CONFIG_SYS_I2C_FSL
226#define CONFIG_SYS_FSL_I2C_SPEED 400000
227#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
228#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
229#define CONFIG_SYS_FSL_I2C2_SPEED 400000
230#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
231#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
232#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
233
234
235#define CONFIG_SYS_I2C_8574_ADDR2 0x20
236
237
238#define CONFIG_SYS_TSEC1_OFFSET 0x24000
239#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
240#define CONFIG_SYS_TSEC2_OFFSET 0x25000
241#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
242
243
244
245
246
247#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
248#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
249#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000
250#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
251#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
252#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000
253#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
254#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
255#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000
256
257#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
258#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
259#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000
260#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
261#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
262#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000
263#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
264#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
265#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000
266
267#if defined(CONFIG_PCI)
268
269#define PCI_64BIT
270#define PCI_ONE_PCI1
271#if defined(PCI_64BIT)
272#undef PCI_ALL_PCI1
273#undef PCI_TWO_PCI1
274#undef PCI_ONE_PCI1
275#endif
276
277#ifndef VME_CADDY2
278#endif
279#define CONFIG_PCI_PNP
280
281#undef CONFIG_EEPRO100
282#undef CONFIG_TULIP
283
284#if !defined(CONFIG_PCI_PNP)
285 #define PCI_ENET0_IOADDR 0xFIXME
286 #define PCI_ENET0_MEMADDR 0xFIXME
287 #define PCI_IDSEL_NUMBER 0xFIXME
288#endif
289
290#define CONFIG_PCI_SCAN_SHOW
291#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957
292
293#endif
294
295
296
297
298#ifdef VME_CADDY2
299#define CONFIG_E1000
300#else
301#define CONFIG_TSEC_ENET
302#endif
303
304#if defined(CONFIG_TSEC_ENET)
305
306#define CONFIG_GMII
307#define CONFIG_TSEC1
308#define CONFIG_TSEC1_NAME "TSEC0"
309#define CONFIG_TSEC2
310#define CONFIG_TSEC2_NAME "TSEC1"
311#define CONFIG_PHY_M88E1111
312#define TSEC1_PHY_ADDR 0x08
313#define TSEC2_PHY_ADDR 0x10
314#define TSEC1_PHYIDX 0
315#define TSEC2_PHYIDX 0
316#define TSEC1_FLAGS TSEC_GIGABIT
317#define TSEC2_FLAGS TSEC_GIGABIT
318
319
320#define CONFIG_ETHPRIME "TSEC0"
321
322#endif
323
324
325
326
327#ifndef CONFIG_SYS_RAMBOOT
328 #define CONFIG_ENV_IS_IN_FLASH
329 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0xc0000)
330 #define CONFIG_ENV_SECT_SIZE 0x20000
331 #define CONFIG_ENV_SIZE 0x2000
332
333
334#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
335#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
336
337#else
338 #define CONFIG_SYS_NO_FLASH
339 #define CONFIG_ENV_IS_NOWHERE
340 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
341 #define CONFIG_ENV_SIZE 0x2000
342#endif
343
344#define CONFIG_LOADS_ECHO
345#define CONFIG_SYS_LOADS_BAUD_CHANGE
346
347
348
349
350#define CONFIG_BOOTP_BOOTFILESIZE
351#define CONFIG_BOOTP_BOOTPATH
352#define CONFIG_BOOTP_GATEWAY
353#define CONFIG_BOOTP_HOSTNAME
354
355
356
357
358#include <config_cmd_default.h>
359
360#define CONFIG_CMD_I2C
361#define CONFIG_CMD_MII
362#define CONFIG_CMD_PING
363#define CONFIG_CMD_DATE
364#define CONFIG_SYS_RTC_BUS_NUM 0x01
365#define CONFIG_SYS_I2C_RTC_ADDR 0x32
366#define CONFIG_RTC_RX8025
367#define CONFIG_CMD_TSI148
368
369#if defined(CONFIG_PCI)
370 #define CONFIG_CMD_PCI
371#endif
372
373#if defined(CONFIG_SYS_RAMBOOT)
374 #undef CONFIG_CMD_ENV
375 #undef CONFIG_CMD_LOADS
376#endif
377
378#define CONFIG_CMD_ELF
379
380#define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0
381
382#undef CONFIG_WATCHDOG
383
384
385
386
387#define CONFIG_SYS_LONGHELP
388#define CONFIG_SYS_LOAD_ADDR 0x2000000
389
390#if defined(CONFIG_CMD_KGDB)
391 #define CONFIG_SYS_CBSIZE 1024
392#else
393 #define CONFIG_SYS_CBSIZE 256
394#endif
395
396#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
397#define CONFIG_SYS_MAXARGS 16
398#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
399
400
401
402
403
404
405#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
406
407#define CONFIG_SYS_RCWH_PCIHOST 0x80000000
408
409#define CONFIG_SYS_HRCW_LOW (\
410 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
411 HRCWL_DDR_TO_SCB_CLK_1X1 |\
412 HRCWL_CSB_TO_CLKIN |\
413 HRCWL_VCO_1X2 |\
414 HRCWL_CORE_TO_CSB_2X1)
415
416#if defined(PCI_64BIT)
417#define CONFIG_SYS_HRCW_HIGH (\
418 HRCWH_PCI_HOST |\
419 HRCWH_64_BIT_PCI |\
420 HRCWH_PCI1_ARBITER_ENABLE |\
421 HRCWH_PCI2_ARBITER_DISABLE |\
422 HRCWH_CORE_ENABLE |\
423 HRCWH_FROM_0X00000100 |\
424 HRCWH_BOOTSEQ_DISABLE |\
425 HRCWH_SW_WATCHDOG_DISABLE |\
426 HRCWH_ROM_LOC_LOCAL_16BIT |\
427 HRCWH_TSEC1M_IN_GMII |\
428 HRCWH_TSEC2M_IN_GMII)
429#else
430#define CONFIG_SYS_HRCW_HIGH (\
431 HRCWH_PCI_HOST |\
432 HRCWH_32_BIT_PCI |\
433 HRCWH_PCI1_ARBITER_ENABLE |\
434 HRCWH_PCI2_ARBITER_ENABLE |\
435 HRCWH_CORE_ENABLE |\
436 HRCWH_FROM_0X00000100 |\
437 HRCWH_BOOTSEQ_DISABLE |\
438 HRCWH_SW_WATCHDOG_DISABLE |\
439 HRCWH_ROM_LOC_LOCAL_16BIT |\
440 HRCWH_TSEC1M_IN_GMII |\
441 HRCWH_TSEC2M_IN_GMII)
442#endif
443
444
445#define CONFIG_SYS_SICRH 0
446#define CONFIG_SYS_SICRL SICRL_LDP_A
447
448#define CONFIG_SYS_HID0_INIT 0x000000000
449#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
450 HID0_ENABLE_INSTRUCTION_CACHE)
451
452#define CONFIG_SYS_HID2 HID2_HBE
453
454#define CONFIG_SYS_GPIO1_PRELIM
455#define CONFIG_SYS_GPIO1_DIR 0x00100000
456#define CONFIG_SYS_GPIO1_DAT 0x00100000
457
458#define CONFIG_SYS_GPIO2_PRELIM
459#define CONFIG_SYS_GPIO2_DIR 0x78900000
460#define CONFIG_SYS_GPIO2_DAT 0x70100000
461
462#define CONFIG_HIGH_BATS
463
464
465#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
466 BATL_MEMCOHERENCE)
467#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
468 BATU_VS | BATU_VP)
469
470
471#ifdef CONFIG_PCI
472#define CONFIG_PCI_INDIRECT_BRIDGE
473#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | \
474 BATL_MEMCOHERENCE)
475#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \
476 BATU_VS | BATU_VP)
477#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | \
478 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
479#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \
480 BATU_VS | BATU_VP)
481#else
482#define CONFIG_SYS_IBAT1L (0)
483#define CONFIG_SYS_IBAT1U (0)
484#define CONFIG_SYS_IBAT2L (0)
485#define CONFIG_SYS_IBAT2U (0)
486#endif
487
488#ifdef CONFIG_MPC83XX_PCI2
489#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_RW | \
490 BATL_MEMCOHERENCE)
491#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \
492 BATU_VS | BATU_VP)
493#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_RW | \
494 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
495#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \
496 BATU_VS | BATU_VP)
497#else
498#define CONFIG_SYS_IBAT3L (0)
499#define CONFIG_SYS_IBAT3U (0)
500#define CONFIG_SYS_IBAT4L (0)
501#define CONFIG_SYS_IBAT4U (0)
502#endif
503
504
505#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_RW | \
506 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
507#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | \
508 BATU_VS | BATU_VP)
509
510#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_MEMCOHERENCE)
511#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
512
513#if (CONFIG_SYS_DDR_SIZE == 512)
514#define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
515 BATL_PP_RW | BATL_MEMCOHERENCE)
516#define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
517 BATU_BL_256M | BATU_VS | BATU_VP)
518#else
519#define CONFIG_SYS_IBAT7L (0)
520#define CONFIG_SYS_IBAT7U (0)
521#endif
522
523#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
524#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
525#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
526#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
527#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
528#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
529#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
530#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
531#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
532#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
533#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
534#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
535#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
536#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
537#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
538#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
539
540#if defined(CONFIG_CMD_KGDB)
541#define CONFIG_KGDB_BAUDRATE 230400
542#endif
543
544
545
546
547#define CONFIG_ENV_OVERWRITE
548
549#if defined(CONFIG_TSEC_ENET)
550#define CONFIG_HAS_ETH0
551#define CONFIG_HAS_ETH1
552#endif
553
554#define CONFIG_HOSTNAME VME8349
555#define CONFIG_ROOTPATH "/tftpboot/rootfs"
556#define CONFIG_BOOTFILE "uImage"
557
558#define CONFIG_LOADADDR 800000
559
560#define CONFIG_BOOTDELAY 6
561#undef CONFIG_BOOTARGS
562
563#define CONFIG_BAUDRATE 9600
564
565#define CONFIG_EXTRA_ENV_SETTINGS \
566 "netdev=eth0\0" \
567 "hostname=vme8349\0" \
568 "nfsargs=setenv bootargs root=/dev/nfs rw " \
569 "nfsroot=${serverip}:${rootpath}\0" \
570 "ramargs=setenv bootargs root=/dev/ram rw\0" \
571 "addip=setenv bootargs ${bootargs} " \
572 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
573 ":${hostname}:${netdev}:off panic=1\0" \
574 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
575 "flash_nfs=run nfsargs addip addtty;" \
576 "bootm ${kernel_addr}\0" \
577 "flash_self=run ramargs addip addtty;" \
578 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
579 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
580 "bootm\0" \
581 "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \
582 "update=protect off fff00000 fff3ffff; " \
583 "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
584 "upd=run load update\0" \
585 "fdtaddr=780000\0" \
586 "fdtfile=vme8349.dtb\0" \
587 ""
588
589#define CONFIG_NFSBOOTCOMMAND \
590 "setenv bootargs root=/dev/nfs rw " \
591 "nfsroot=$serverip:$rootpath " \
592 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
593 "$netdev:off " \
594 "console=$consoledev,$baudrate $othbootargs;" \
595 "tftp $loadaddr $bootfile;" \
596 "tftp $fdtaddr $fdtfile;" \
597 "bootm $loadaddr - $fdtaddr"
598
599#define CONFIG_RAMBOOTCOMMAND \
600 "setenv bootargs root=/dev/ram rw " \
601 "console=$consoledev,$baudrate $othbootargs;" \
602 "tftp $ramdiskaddr $ramdiskfile;" \
603 "tftp $loadaddr $bootfile;" \
604 "tftp $fdtaddr $fdtfile;" \
605 "bootm $loadaddr $ramdiskaddr $fdtaddr"
606
607#define CONFIG_BOOTCOMMAND "run flash_self"
608
609#ifndef __ASSEMBLY__
610int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen,
611 unsigned char *buffer, int len);
612#endif
613
614#endif
615