LXR uboot/arch/arm/cpu/arm926ejs/pantheon/cpu.c

   1/*
   2 * (C) Copyright 2011
   3 * Marvell Semiconductor <www.marvell.com>
   4 * Written-by: Lei Wen <leiwen@marvell.com>
   5 *
   6 * SPDX-License-Identifier:     GPL-2.0+
   7 */
   8
   9#include <common.h>
  10#include <asm/arch/cpu.h>
  11#include <asm/arch/pantheon.h>
  12
  13#define UARTCLK14745KHZ (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
  14#define SET_MRVL_ID     (1<<8)
  15#define L2C_RAM_SEL     (1<<4)
  16
  17int arch_cpu_init(void)
  18{
  19        u32 val;
  20        struct panthcpu_registers *cpuregs =
  21                (struct panthcpu_registers*) PANTHEON_CPU_BASE;
  22
  23        struct panthapb_registers *apbclkres =
  24                (struct panthapb_registers*) PANTHEON_APBC_BASE;
  25
  26        struct panthmpmu_registers *mpmu =
  27                (struct panthmpmu_registers*) PANTHEON_MPMU_BASE;
  28
  29        struct panthapmu_registers *apmu =
  30                (struct panthapmu_registers *) PANTHEON_APMU_BASE;
  31
  32        /* set SEL_MRVL_ID bit in PANTHEON_CPU_CONF register */
  33        val = readl(&cpuregs->cpu_conf);
  34        val = val | SET_MRVL_ID;
  35        writel(val, &cpuregs->cpu_conf);
  36
  37        /* Turn on clock gating (PMUM_CCGR) */
  38        writel(0xFFFFFFFF, &mpmu->ccgr);
  39
  40        /* Turn on clock gating (PMUM_ACGR) */
  41        writel(0xFFFFFFFF, &mpmu->acgr);
  42
  43        /* Turn on uart2 clock */
  44        writel(UARTCLK14745KHZ, &apbclkres->uart0);
  45
  46        /* Enable GPIO clock */
  47        writel(APBC_APBCLK, &apbclkres->gpio);
  48
  49#ifdef CONFIG_I2C_MV
  50        /* Enable I2C clock */
  51        writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apbclkres->twsi);
  52        writel(APBC_FNCLK | APBC_APBCLK, &apbclkres->twsi);
  53#endif
  54
  55#ifdef CONFIG_MV_SDHCI
  56        /* Enable mmc clock */
  57        writel(APMU_PERI_CLK | APMU_AXI_CLK | APMU_PERI_RST | APMU_AXI_RST,
  58                        &apmu->sd1);
  59        writel(APMU_PERI_CLK | APMU_AXI_CLK | APMU_PERI_RST | APMU_AXI_RST,
  60                        &apmu->sd3);
  61#endif
  62
  63        icache_enable();
  64
  65        return 0;
  66}
  67
  68#if defined(CONFIG_DISPLAY_CPUINFO)
  69int print_cpuinfo(void)
  70{
  71        u32 id;
  72        struct panthcpu_registers *cpuregs =
  73                (struct panthcpu_registers*) PANTHEON_CPU_BASE;
  74
  75        id = readl(&cpuregs->chip_id);
  76        printf("SoC:   PANTHEON 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10));
  77        return 0;
  78}
  79#endif
  80
  81#ifdef CONFIG_I2C_MV
  82void i2c_clk_enable(void)
  83{
  84}
  85#endif
  86