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17#include <config.h>
18
19#ifdef CONFIG_USB_OHCI
20
21
22
23#include <common.h>
24#include <malloc.h>
25#include <asm/io.h>
26#include <asm/au1x00.h>
27#include <usb.h>
28#include "au1x00_usb_ohci.h"
29
30#define OHCI_USE_NPS
31#define OHCI_VERBOSE_DEBUG
32#define OHCI_FILL_TRACE
33
34#define USBH_ENABLE_BE (1<<0)
35#define USBH_ENABLE_C (1<<1)
36#define USBH_ENABLE_E (1<<2)
37#define USBH_ENABLE_CE (1<<3)
38#define USBH_ENABLE_RD (1<<4)
39
40#ifdef __LITTLE_ENDIAN
41#define USBH_ENABLE_INIT (USBH_ENABLE_CE | USBH_ENABLE_E | USBH_ENABLE_C)
42#else
43#define USBH_ENABLE_INIT (USBH_ENABLE_CE | USBH_ENABLE_E | USBH_ENABLE_C | USBH_ENABLE_BE)
44#endif
45
46
47
48#define OHCI_CONTROL_INIT \
49 (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
50
51#undef readl
52#undef writel
53
54#define readl(a) au_readl((long)(a))
55#define writel(v,a) au_writel((v),(int)(a))
56
57#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
58
59#define DEBUG
60#ifdef DEBUG
61#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
62#else
63#define dbg(format, arg...) do {} while(0)
64#endif
65#define err(format, arg...) printf("ERROR: " format "\n", ## arg)
66#define SHOW_INFO
67#ifdef SHOW_INFO
68#define info(format, arg...) printf("INFO: " format "\n", ## arg)
69#else
70#define info(format, arg...) do {} while(0)
71#endif
72
73#define m16_swap(x) swap_16(x)
74#define m32_swap(x) swap_32(x)
75
76
77static ohci_t gohci;
78
79struct ohci_hcca ghcca[1];
80
81struct ohci_hcca *phcca;
82
83struct ohci_device ohci_dev;
84
85urb_priv_t urb_priv;
86
87int got_rhsc;
88
89struct usb_device *devgone;
90
91
92
93
94
95
96
97#define OHCI_QUIRK_AMD756 0xabcd
98#define read_roothub(hc, register, mask) ({ \
99 u32 temp = readl (&hc->regs->roothub.register); \
100 if (hc->flags & OHCI_QUIRK_AMD756) \
101 while (temp & mask) \
102 temp = readl (&hc->regs->roothub.register); \
103 temp; })
104
105static u32 roothub_a (struct ohci *hc)
106 { return read_roothub (hc, a, 0xfc0fe000); }
107static inline u32 roothub_b (struct ohci *hc)
108 { return readl (&hc->regs->roothub.b); }
109static inline u32 roothub_status (struct ohci *hc)
110 { return readl (&hc->regs->roothub.status); }
111static u32 roothub_portstatus (struct ohci *hc, int i)
112 { return read_roothub (hc, portstatus [i], 0xffe0fce0); }
113
114
115
116static int hc_interrupt (void);
117static void
118td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer,
119 int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval);
120
121
122
123
124
125
126
127static void urb_free_priv (urb_priv_t * urb)
128{
129 int i;
130 int last;
131 struct td * td;
132
133 last = urb->length - 1;
134 if (last >= 0) {
135 for (i = 0; i <= last; i++) {
136 td = urb->td[i];
137 if (td) {
138 td->usb_dev = NULL;
139 urb->td[i] = NULL;
140 }
141 }
142 }
143}
144
145
146
147#ifdef DEBUG
148static int sohci_get_current_frame_number (struct usb_device * dev);
149
150
151
152
153static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer,
154 int transfer_len, struct devrequest * setup, char * str, int small)
155{
156 urb_priv_t * purb = &urb_priv;
157
158 dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
159 str,
160 sohci_get_current_frame_number (dev),
161 usb_pipedevice (pipe),
162 usb_pipeendpoint (pipe),
163 usb_pipeout (pipe)? 'O': 'I',
164 usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):
165 (usb_pipecontrol (pipe)? "CTRL": "BULK"),
166 purb->actual_length,
167 transfer_len, dev->status);
168#ifdef OHCI_VERBOSE_DEBUG
169 if (!small) {
170 int i, len;
171
172 if (usb_pipecontrol (pipe)) {
173 printf (__FILE__ ": cmd(8):");
174 for (i = 0; i < 8 ; i++)
175 printf (" %02x", ((__u8 *) setup) [i]);
176 printf ("\n");
177 }
178 if (transfer_len > 0 && buffer) {
179 printf (__FILE__ ": data(%d/%d):",
180 purb->actual_length,
181 transfer_len);
182 len = usb_pipeout (pipe)?
183 transfer_len: purb->actual_length;
184 for (i = 0; i < 16 && i < len; i++)
185 printf (" %02x", ((__u8 *) buffer) [i]);
186 printf ("%s\n", i < len? "...": "");
187 }
188 }
189#endif
190}
191
192
193void ep_print_int_eds (ohci_t *ohci, char * str) {
194 int i, j;
195 __u32 * ed_p;
196 for (i= 0; i < 32; i++) {
197 j = 5;
198 ed_p = &(ohci->hcca->int_table [i]);
199 if (*ed_p == 0)
200 continue;
201 printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i);
202 while (*ed_p != 0 && j--) {
203 ed_t *ed = (ed_t *)m32_swap(ed_p);
204 printf (" ed: %4x;", ed->hwINFO);
205 ed_p = &ed->hwNextED;
206 }
207 printf ("\n");
208 }
209}
210
211static void ohci_dump_intr_mask (char *label, __u32 mask)
212{
213 dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
214 label,
215 mask,
216 (mask & OHCI_INTR_MIE) ? " MIE" : "",
217 (mask & OHCI_INTR_OC) ? " OC" : "",
218 (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
219 (mask & OHCI_INTR_FNO) ? " FNO" : "",
220 (mask & OHCI_INTR_UE) ? " UE" : "",
221 (mask & OHCI_INTR_RD) ? " RD" : "",
222 (mask & OHCI_INTR_SF) ? " SF" : "",
223 (mask & OHCI_INTR_WDH) ? " WDH" : "",
224 (mask & OHCI_INTR_SO) ? " SO" : ""
225 );
226}
227
228static void maybe_print_eds (char *label, __u32 value)
229{
230 ed_t *edp = (ed_t *)value;
231
232 if (value) {
233 dbg ("%s %08x", label, value);
234 dbg ("%08x", edp->hwINFO);
235 dbg ("%08x", edp->hwTailP);
236 dbg ("%08x", edp->hwHeadP);
237 dbg ("%08x", edp->hwNextED);
238 }
239}
240
241static char * hcfs2string (int state)
242{
243 switch (state) {
244 case OHCI_USB_RESET: return "reset";
245 case OHCI_USB_RESUME: return "resume";
246 case OHCI_USB_OPER: return "operational";
247 case OHCI_USB_SUSPEND: return "suspend";
248 }
249 return "?";
250}
251
252
253static void ohci_dump_status (ohci_t *controller)
254{
255 struct ohci_regs *regs = controller->regs;
256 __u32 temp;
257
258 temp = readl (®s->revision) & 0xff;
259 if (temp != 0x10)
260 dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f));
261
262 temp = readl (®s->control);
263 dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
264 (temp & OHCI_CTRL_RWE) ? " RWE" : "",
265 (temp & OHCI_CTRL_RWC) ? " RWC" : "",
266 (temp & OHCI_CTRL_IR) ? " IR" : "",
267 hcfs2string (temp & OHCI_CTRL_HCFS),
268 (temp & OHCI_CTRL_BLE) ? " BLE" : "",
269 (temp & OHCI_CTRL_CLE) ? " CLE" : "",
270 (temp & OHCI_CTRL_IE) ? " IE" : "",
271 (temp & OHCI_CTRL_PLE) ? " PLE" : "",
272 temp & OHCI_CTRL_CBSR
273 );
274
275 temp = readl (®s->cmdstatus);
276 dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
277 (temp & OHCI_SOC) >> 16,
278 (temp & OHCI_OCR) ? " OCR" : "",
279 (temp & OHCI_BLF) ? " BLF" : "",
280 (temp & OHCI_CLF) ? " CLF" : "",
281 (temp & OHCI_HCR) ? " HCR" : ""
282 );
283
284 ohci_dump_intr_mask ("intrstatus", readl (®s->intrstatus));
285 ohci_dump_intr_mask ("intrenable", readl (®s->intrenable));
286
287 maybe_print_eds ("ed_periodcurrent", readl (®s->ed_periodcurrent));
288
289 maybe_print_eds ("ed_controlhead", readl (®s->ed_controlhead));
290 maybe_print_eds ("ed_controlcurrent", readl (®s->ed_controlcurrent));
291
292 maybe_print_eds ("ed_bulkhead", readl (®s->ed_bulkhead));
293 maybe_print_eds ("ed_bulkcurrent", readl (®s->ed_bulkcurrent));
294
295 maybe_print_eds ("donehead", readl (®s->donehead));
296}
297
298static void ohci_dump_roothub (ohci_t *controller, int verbose)
299{
300 __u32 temp, ndp, i;
301
302 temp = roothub_a (controller);
303 ndp = (temp & RH_A_NDP);
304
305 if (verbose) {
306 dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
307 ((temp & RH_A_POTPGT) >> 24) & 0xff,
308 (temp & RH_A_NOCP) ? " NOCP" : "",
309 (temp & RH_A_OCPM) ? " OCPM" : "",
310 (temp & RH_A_DT) ? " DT" : "",
311 (temp & RH_A_NPS) ? " NPS" : "",
312 (temp & RH_A_PSM) ? " PSM" : "",
313 ndp
314 );
315 temp = roothub_b (controller);
316 dbg ("roothub.b: %08x PPCM=%04x DR=%04x",
317 temp,
318 (temp & RH_B_PPCM) >> 16,
319 (temp & RH_B_DR)
320 );
321 temp = roothub_status (controller);
322 dbg ("roothub.status: %08x%s%s%s%s%s%s",
323 temp,
324 (temp & RH_HS_CRWE) ? " CRWE" : "",
325 (temp & RH_HS_OCIC) ? " OCIC" : "",
326 (temp & RH_HS_LPSC) ? " LPSC" : "",
327 (temp & RH_HS_DRWE) ? " DRWE" : "",
328 (temp & RH_HS_OCI) ? " OCI" : "",
329 (temp & RH_HS_LPS) ? " LPS" : ""
330 );
331 }
332
333 for (i = 0; i < ndp; i++) {
334 temp = roothub_portstatus (controller, i);
335 dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
336 i,
337 temp,
338 (temp & RH_PS_PRSC) ? " PRSC" : "",
339 (temp & RH_PS_OCIC) ? " OCIC" : "",
340 (temp & RH_PS_PSSC) ? " PSSC" : "",
341 (temp & RH_PS_PESC) ? " PESC" : "",
342 (temp & RH_PS_CSC) ? " CSC" : "",
343
344 (temp & RH_PS_LSDA) ? " LSDA" : "",
345 (temp & RH_PS_PPS) ? " PPS" : "",
346 (temp & RH_PS_PRS) ? " PRS" : "",
347 (temp & RH_PS_POCI) ? " POCI" : "",
348 (temp & RH_PS_PSS) ? " PSS" : "",
349
350 (temp & RH_PS_PES) ? " PES" : "",
351 (temp & RH_PS_CCS) ? " CCS" : ""
352 );
353 }
354}
355
356static void ohci_dump (ohci_t *controller, int verbose)
357{
358 dbg ("OHCI controller usb-%s state", controller->slot_name);
359
360
361 ohci_dump_status (controller);
362 if (verbose)
363 ep_print_int_eds (controller, "hcca");
364 dbg ("hcca frame #%04x", controller->hcca->frame_no);
365 ohci_dump_roothub (controller, 1);
366}
367
368
369#endif
370
371
372
373
374
375
376
377int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer,
378 int transfer_len, struct devrequest *setup, int interval)
379{
380 ohci_t *ohci;
381 ed_t * ed;
382 urb_priv_t *purb_priv;
383 int i, size = 0;
384
385 ohci = &gohci;
386
387
388
389 if (ohci->disabled) {
390 err("sohci_submit_job: EPIPE");
391 return -1;
392 }
393
394
395 if (!(ed = ep_add_ed (dev, pipe))) {
396 err("sohci_submit_job: ENOMEM");
397 return -1;
398 }
399
400
401 switch (usb_pipetype (pipe)) {
402 case PIPE_BULK:
403 size = (transfer_len - 1) / 4096 + 1;
404 break;
405 case PIPE_CONTROL:
406 size = (transfer_len == 0)? 2:
407 (transfer_len - 1) / 4096 + 3;
408 break;
409 }
410
411 if (size >= (N_URB_TD - 1)) {
412 err("need %d TDs, only have %d", size, N_URB_TD);
413 return -1;
414 }
415 purb_priv = &urb_priv;
416 purb_priv->pipe = pipe;
417
418
419 purb_priv->length = size;
420 purb_priv->ed = ed;
421 purb_priv->actual_length = 0;
422
423
424
425 for (i = 0; i < size; i++) {
426 purb_priv->td[i] = td_alloc (dev);
427 if (!purb_priv->td[i]) {
428 purb_priv->length = i;
429 urb_free_priv (purb_priv);
430 err("sohci_submit_job: ENOMEM");
431 return -1;
432 }
433 }
434
435 if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
436 urb_free_priv (purb_priv);
437 err("sohci_submit_job: EINVAL");
438 return -1;
439 }
440
441
442 if (ed->state != ED_OPER)
443 ep_link (ohci, ed);
444
445
446 td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval);
447
448 return 0;
449}
450
451
452
453#ifdef DEBUG
454
455
456static int sohci_get_current_frame_number (struct usb_device *usb_dev)
457{
458 ohci_t *ohci = &gohci;
459
460 return m16_swap (ohci->hcca->frame_no);
461}
462#endif
463
464
465
466
467
468
469
470static int ep_link (ohci_t *ohci, ed_t *edi)
471{
472 volatile ed_t *ed = edi;
473
474 ed->state = ED_OPER;
475
476 switch (ed->type) {
477 case PIPE_CONTROL:
478 ed->hwNextED = 0;
479 if (ohci->ed_controltail == NULL) {
480 writel ((long)ed, &ohci->regs->ed_controlhead);
481 } else {
482 ohci->ed_controltail->hwNextED = m32_swap (ed);
483 }
484 ed->ed_prev = ohci->ed_controltail;
485 if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
486 !ohci->ed_rm_list[1] && !ohci->sleeping) {
487 ohci->hc_control |= OHCI_CTRL_CLE;
488 writel (ohci->hc_control, &ohci->regs->control);
489 }
490 ohci->ed_controltail = edi;
491 break;
492
493 case PIPE_BULK:
494 ed->hwNextED = 0;
495 if (ohci->ed_bulktail == NULL) {
496 writel ((long)ed, &ohci->regs->ed_bulkhead);
497 } else {
498 ohci->ed_bulktail->hwNextED = m32_swap (ed);
499 }
500 ed->ed_prev = ohci->ed_bulktail;
501 if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
502 !ohci->ed_rm_list[1] && !ohci->sleeping) {
503 ohci->hc_control |= OHCI_CTRL_BLE;
504 writel (ohci->hc_control, &ohci->regs->control);
505 }
506 ohci->ed_bulktail = edi;
507 break;
508 }
509 return 0;
510}
511
512
513
514
515
516
517
518
519static int ep_unlink (ohci_t *ohci, ed_t *ed)
520{
521 ed->hwINFO |= m32_swap (OHCI_ED_SKIP);
522
523 switch (ed->type) {
524 case PIPE_CONTROL:
525 if (ed->ed_prev == NULL) {
526 if (!ed->hwNextED) {
527 ohci->hc_control &= ~OHCI_CTRL_CLE;
528 writel (ohci->hc_control, &ohci->regs->control);
529 }
530 writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead);
531 } else {
532 ed->ed_prev->hwNextED = ed->hwNextED;
533 }
534 if (ohci->ed_controltail == ed) {
535 ohci->ed_controltail = ed->ed_prev;
536 } else {
537 ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
538 }
539 break;
540
541 case PIPE_BULK:
542 if (ed->ed_prev == NULL) {
543 if (!ed->hwNextED) {
544 ohci->hc_control &= ~OHCI_CTRL_BLE;
545 writel (ohci->hc_control, &ohci->regs->control);
546 }
547 writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead);
548 } else {
549 ed->ed_prev->hwNextED = ed->hwNextED;
550 }
551 if (ohci->ed_bulktail == ed) {
552 ohci->ed_bulktail = ed->ed_prev;
553 } else {
554 ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
555 }
556 break;
557 }
558 ed->state = ED_UNLINK;
559 return 0;
560}
561
562
563
564
565
566
567
568
569
570
571static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe)
572{
573 td_t *td;
574 ed_t *ed_ret;
575 volatile ed_t *ed;
576
577 ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) |
578 (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))];
579
580 if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
581 err("ep_add_ed: pending delete");
582
583 return NULL;
584 }
585
586 if (ed->state == ED_NEW) {
587 ed->hwINFO = m32_swap (OHCI_ED_SKIP);
588
589 td = td_alloc (usb_dev);
590 ed->hwTailP = m32_swap (td);
591 ed->hwHeadP = ed->hwTailP;
592 ed->state = ED_UNLINK;
593 ed->type = usb_pipetype (pipe);
594 ohci_dev.ed_cnt++;
595 }
596
597 ed->hwINFO = m32_swap (usb_pipedevice (pipe)
598 | usb_pipeendpoint (pipe) << 7
599 | (usb_pipeisoc (pipe)? 0x8000: 0)
600 | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000))
601 | (usb_dev->speed == USB_SPEED_LOW) << 13
602 | usb_maxpacket (usb_dev, pipe) << 16);
603
604 return ed_ret;
605}
606
607
608
609
610
611
612
613static void td_fill (ohci_t *ohci, unsigned int info,
614 void *data, int len,
615 struct usb_device *dev, int index, urb_priv_t *urb_priv)
616{
617 volatile td_t *td, *td_pt;
618#ifdef OHCI_FILL_TRACE
619 int i;
620#endif
621
622 if (index > urb_priv->length) {
623 err("index > length");
624 return;
625 }
626
627 td_pt = urb_priv->td [index];
628 td_pt->hwNextTD = 0;
629
630
631 td = urb_priv->td [index] = (td_t *)(m32_swap (urb_priv->ed->hwTailP) & ~0xf);
632
633 td->ed = urb_priv->ed;
634 td->next_dl_td = NULL;
635 td->index = index;
636 td->data = (__u32)data;
637#ifdef OHCI_FILL_TRACE
638 if (1 || (usb_pipebulk(urb_priv->pipe) &&
639 usb_pipeout(urb_priv->pipe))) {
640 for (i = 0; i < len; i++)
641 printf("td->data[%d] %#2x\n",i, ((unsigned char *)(td->data+0x80000000))[i]);
642 }
643#endif
644 if (!len)
645 data = 0;
646
647 td->hwINFO = m32_swap (info);
648 td->hwCBP = m32_swap (data);
649 if (data)
650 td->hwBE = m32_swap (data + len - 1);
651 else
652 td->hwBE = 0;
653 td->hwNextTD = m32_swap (td_pt);
654 td->hwPSW [0] = m16_swap (((__u32)data & 0x0FFF) | 0xE000);
655
656
657 td->ed->hwTailP = td->hwNextTD;
658}
659
660
661
662
663
664#define kseg_to_phys(x) ((void *)((__u32)(x) - 0x80000000))
665
666static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer,
667 int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval)
668{
669 ohci_t *ohci = &gohci;
670 int data_len = transfer_len;
671 void *data;
672 int cnt = 0;
673 __u32 info = 0;
674 unsigned int toggle = 0;
675
676
677 if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
678 toggle = TD_T_TOGGLE;
679 } else {
680 toggle = TD_T_DATA0;
681 usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1);
682 }
683 urb->td_cnt = 0;
684 if (data_len)
685 data = kseg_to_phys(buffer);
686 else
687 data = 0;
688
689 switch (usb_pipetype (pipe)) {
690 case PIPE_BULK:
691 info = usb_pipeout (pipe)?
692 TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ;
693 while(data_len > 4096) {
694 td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb);
695 data += 4096; data_len -= 4096; cnt++;
696 }
697 info = usb_pipeout (pipe)?
698 TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ;
699 td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb);
700 cnt++;
701
702 if (!ohci->sleeping)
703 writel (OHCI_BLF, &ohci->regs->cmdstatus);
704 break;
705
706 case PIPE_CONTROL:
707 info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
708 td_fill (ohci, info, kseg_to_phys(setup), 8, dev, cnt++, urb);
709 if (data_len > 0) {
710 info = usb_pipeout (pipe)?
711 TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
712
713 td_fill (ohci, info, data, data_len, dev, cnt++, urb);
714 }
715 info = usb_pipeout (pipe)?
716 TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1;
717 td_fill (ohci, info, data, 0, dev, cnt++, urb);
718 if (!ohci->sleeping)
719 writel (OHCI_CLF, &ohci->regs->cmdstatus);
720 break;
721 }
722 if (urb->length != cnt)
723 dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
724}
725
726
727
728
729
730
731
732
733static void dl_transfer_length(td_t * td)
734{
735 __u32 tdINFO, tdBE, tdCBP;
736 urb_priv_t *lurb_priv = &urb_priv;
737
738 tdINFO = m32_swap (td->hwINFO);
739 tdBE = m32_swap (td->hwBE);
740 tdCBP = m32_swap (td->hwCBP);
741
742
743 if (!(usb_pipecontrol(lurb_priv->pipe) &&
744 ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
745 if (tdBE != 0) {
746 if (td->hwCBP == 0)
747 lurb_priv->actual_length += tdBE - td->data + 1;
748 else
749 lurb_priv->actual_length += tdCBP - td->data;
750 }
751 }
752}
753
754
755
756
757
758
759static td_t * dl_reverse_done_list (ohci_t *ohci)
760{
761 __u32 td_list_hc;
762 td_t *td_rev = NULL;
763 td_t *td_list = NULL;
764 urb_priv_t *lurb_priv = NULL;
765
766 td_list_hc = m32_swap (ohci->hcca->done_head) & 0xfffffff0;
767 ohci->hcca->done_head = 0;
768
769 while (td_list_hc) {
770 td_list = (td_t *)td_list_hc;
771
772 if (TD_CC_GET (m32_swap (td_list->hwINFO))) {
773 lurb_priv = &urb_priv;
774 dbg(" USB-error/status: %x : %p",
775 TD_CC_GET (m32_swap (td_list->hwINFO)), td_list);
776 if (td_list->ed->hwHeadP & m32_swap (0x1)) {
777 if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) {
778 td_list->ed->hwHeadP =
779 (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & m32_swap (0xfffffff0)) |
780 (td_list->ed->hwHeadP & m32_swap (0x2));
781 lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1;
782 } else
783 td_list->ed->hwHeadP &= m32_swap (0xfffffff2);
784 }
785 }
786
787 td_list->next_dl_td = td_rev;
788 td_rev = td_list;
789 td_list_hc = m32_swap (td_list->hwNextTD) & 0xfffffff0;
790 }
791 return td_list;
792}
793
794
795
796
797static int dl_done_list (ohci_t *ohci, td_t *td_list)
798{
799 td_t *td_list_next = NULL;
800 ed_t *ed;
801 int cc = 0;
802 int stat = 0;
803
804 urb_priv_t *lurb_priv;
805 __u32 tdINFO, edHeadP, edTailP;
806
807 while (td_list) {
808 td_list_next = td_list->next_dl_td;
809
810 lurb_priv = &urb_priv;
811 tdINFO = m32_swap (td_list->hwINFO);
812
813 ed = td_list->ed;
814
815 dl_transfer_length(td_list);
816
817
818 cc = TD_CC_GET (tdINFO);
819 if (cc != 0) {
820 dbg("ConditionCode %#x", cc);
821 stat = cc_to_error[cc];
822 }
823
824 if (ed->state != ED_NEW) {
825 edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0;
826 edTailP = m32_swap (ed->hwTailP);
827
828
829 if ((edHeadP == edTailP) && (ed->state == ED_OPER))
830 ep_unlink (ohci, ed);
831 }
832
833 td_list = td_list_next;
834 }
835 return stat;
836}
837
838
839
840
841
842#include <usbroothubdes.h>
843
844
845
846
847
848
849#define OK(x) len = (x); break
850#ifdef DEBUG
851#define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);}
852#define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);}
853#else
854#define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status)
855#define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
856#endif
857#define RD_RH_STAT roothub_status(&gohci)
858#define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1)
859
860
861
862int rh_check_port_status(ohci_t *controller)
863{
864 __u32 temp, ndp, i;
865 int res;
866
867 res = -1;
868 temp = roothub_a (controller);
869 ndp = (temp & RH_A_NDP);
870 for (i = 0; i < ndp; i++) {
871 temp = roothub_portstatus (controller, i);
872
873 if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
874 (RH_PS_PESC | RH_PS_CSC)) &&
875 ((temp & RH_PS_CCS) == 0)) {
876 res = i;
877 break;
878 }
879 }
880 return res;
881}
882
883static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
884 void *buffer, int transfer_len, struct devrequest *cmd)
885{
886 void * data = buffer;
887 int leni = transfer_len;
888 int len = 0;
889 int stat = 0;
890 __u32 datab[4];
891 __u8 *data_buf = (__u8 *)datab;
892 __u16 bmRType_bReq;
893 __u16 wValue;
894 __u16 wIndex;
895 __u16 wLength;
896
897#ifdef DEBUG
898urb_priv.actual_length = 0;
899pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
900#else
901 mdelay(1);
902#endif
903 if (usb_pipeint(pipe)) {
904 info("Root-Hub submit IRQ: NOT implemented");
905 return 0;
906 }
907
908 bmRType_bReq = cmd->requesttype | (cmd->request << 8);
909 wValue = m16_swap (cmd->value);
910 wIndex = m16_swap (cmd->index);
911 wLength = m16_swap (cmd->length);
912
913 info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
914 dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
915
916 switch (bmRType_bReq) {
917
918
919
920
921
922
923
924
925 case RH_GET_STATUS:
926 *(__u16 *) data_buf = m16_swap (1); OK (2);
927 case RH_GET_STATUS | RH_INTERFACE:
928 *(__u16 *) data_buf = m16_swap (0); OK (2);
929 case RH_GET_STATUS | RH_ENDPOINT:
930 *(__u16 *) data_buf = m16_swap (0); OK (2);
931 case RH_GET_STATUS | RH_CLASS:
932 *(__u32 *) data_buf = m32_swap (
933 RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
934 OK (4);
935 case RH_GET_STATUS | RH_OTHER | RH_CLASS:
936 *(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4);
937
938 case RH_CLEAR_FEATURE | RH_ENDPOINT:
939 switch (wValue) {
940 case (RH_ENDPOINT_STALL): OK (0);
941 }
942 break;
943
944 case RH_CLEAR_FEATURE | RH_CLASS:
945 switch (wValue) {
946 case RH_C_HUB_LOCAL_POWER:
947 OK(0);
948 case (RH_C_HUB_OVER_CURRENT):
949 WR_RH_STAT(RH_HS_OCIC); OK (0);
950 }
951 break;
952
953 case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
954 switch (wValue) {
955 case (RH_PORT_ENABLE):
956 WR_RH_PORTSTAT (RH_PS_CCS ); OK (0);
957 case (RH_PORT_SUSPEND):
958 WR_RH_PORTSTAT (RH_PS_POCI); OK (0);
959 case (RH_PORT_POWER):
960 WR_RH_PORTSTAT (RH_PS_LSDA); OK (0);
961 case (RH_C_PORT_CONNECTION):
962 WR_RH_PORTSTAT (RH_PS_CSC ); OK (0);
963 case (RH_C_PORT_ENABLE):
964 WR_RH_PORTSTAT (RH_PS_PESC); OK (0);
965 case (RH_C_PORT_SUSPEND):
966 WR_RH_PORTSTAT (RH_PS_PSSC); OK (0);
967 case (RH_C_PORT_OVER_CURRENT):
968 WR_RH_PORTSTAT (RH_PS_OCIC); OK (0);
969 case (RH_C_PORT_RESET):
970 WR_RH_PORTSTAT (RH_PS_PRSC); OK (0);
971 }
972 break;
973
974 case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
975 switch (wValue) {
976 case (RH_PORT_SUSPEND):
977 WR_RH_PORTSTAT (RH_PS_PSS ); OK (0);
978 case (RH_PORT_RESET):
979 if (RD_RH_PORTSTAT & RH_PS_CCS)
980 WR_RH_PORTSTAT (RH_PS_PRS);
981 OK (0);
982 case (RH_PORT_POWER):
983 WR_RH_PORTSTAT (RH_PS_PPS ); OK (0);
984 case (RH_PORT_ENABLE):
985 if (RD_RH_PORTSTAT & RH_PS_CCS)
986 WR_RH_PORTSTAT (RH_PS_PES );
987 OK (0);
988 }
989 break;
990
991 case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0);
992
993 case RH_GET_DESCRIPTOR:
994 switch ((wValue & 0xff00) >> 8) {
995 case (0x01):
996 len = min_t(unsigned int,
997 leni,
998 min_t(unsigned int,
999 sizeof (root_hub_dev_des),
1000 wLength));
1001 data_buf = root_hub_dev_des; OK(len);
1002 case (0x02):
1003 len = min_t(unsigned int,
1004 leni,
1005 min_t(unsigned int,
1006 sizeof (root_hub_config_des),
1007 wLength));
1008 data_buf = root_hub_config_des; OK(len);
1009 case (0x03):
1010 if(wValue==0x0300) {
1011 len = min_t(unsigned int,
1012 leni,
1013 min_t(unsigned int,
1014 sizeof (root_hub_str_index0),
1015 wLength));
1016 data_buf = root_hub_str_index0;
1017 OK(len);
1018 }
1019 if(wValue==0x0301) {
1020 len = min_t(unsigned int,
1021 leni,
1022 min_t(unsigned int,
1023 sizeof (root_hub_str_index1),
1024 wLength));
1025 data_buf = root_hub_str_index1;
1026 OK(len);
1027 }
1028 default:
1029 stat = USB_ST_STALLED;
1030 }
1031 break;
1032
1033 case RH_GET_DESCRIPTOR | RH_CLASS:
1034 {
1035 __u32 temp = roothub_a (&gohci);
1036
1037 data_buf [0] = 9;
1038 data_buf [1] = 0x29;
1039 data_buf [2] = temp & RH_A_NDP;
1040 data_buf [3] = 0;
1041 if (temp & RH_A_PSM)
1042 data_buf [3] |= 0x1;
1043 if (temp & RH_A_NOCP)
1044 data_buf [3] |= 0x10;
1045 else if (temp & RH_A_OCPM)
1046 data_buf [3] |= 0x8;
1047
1048
1049 datab [1] = 0;
1050 data_buf [5] = (temp & RH_A_POTPGT) >> 24;
1051 temp = roothub_b (&gohci);
1052 data_buf [7] = temp & RH_B_DR;
1053 if (data_buf [2] < 7) {
1054 data_buf [8] = 0xff;
1055 } else {
1056 data_buf [0] += 2;
1057 data_buf [8] = (temp & RH_B_DR) >> 8;
1058 data_buf [10] = data_buf [9] = 0xff;
1059 }
1060
1061 len = min_t(unsigned int, leni,
1062 min_t(unsigned int, data_buf [0], wLength));
1063 OK (len);
1064 }
1065
1066 case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1);
1067
1068 case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0);
1069
1070 default:
1071 dbg ("unsupported root hub command");
1072 stat = USB_ST_STALLED;
1073 }
1074
1075#ifdef DEBUG
1076 ohci_dump_roothub (&gohci, 1);
1077#else
1078 mdelay(1);
1079#endif
1080
1081 len = min_t(int, len, leni);
1082 if (data != data_buf)
1083 memcpy (data, data_buf, len);
1084 dev->act_len = len;
1085 dev->status = stat;
1086
1087#ifdef DEBUG
1088 if (transfer_len)
1089 urb_priv.actual_length = transfer_len;
1090 pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0);
1091#else
1092 mdelay(1);
1093#endif
1094
1095 return stat;
1096}
1097
1098
1099
1100
1101
1102int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1103 int transfer_len, struct devrequest *setup, int interval)
1104{
1105 int stat = 0;
1106 int maxsize = usb_maxpacket(dev, pipe);
1107 int timeout;
1108
1109
1110 if (devgone == dev) {
1111 dev->status = USB_ST_CRC_ERR;
1112 return 0;
1113 }
1114
1115#ifdef DEBUG
1116 urb_priv.actual_length = 0;
1117 pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
1118#else
1119 mdelay(1);
1120#endif
1121 if (!maxsize) {
1122 err("submit_common_message: pipesize for pipe %lx is zero",
1123 pipe);
1124 return -1;
1125 }
1126
1127 if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) {
1128 err("sohci_submit_job failed");
1129 return -1;
1130 }
1131
1132 mdelay(10);
1133
1134
1135
1136#define BULK_TO 5000
1137 if (usb_pipebulk(pipe))
1138 timeout = BULK_TO;
1139 else
1140 timeout = 100;
1141
1142 timeout *= 4;
1143
1144 for (;;) {
1145
1146 stat = hc_interrupt();
1147 if (stat < 0) {
1148 stat = USB_ST_CRC_ERR;
1149 break;
1150 }
1151 if (stat >= 0 && stat != 0xff) {
1152
1153 break;
1154 }
1155 if (--timeout) {
1156 udelay(250);
1157 } else {
1158 err("CTL:TIMEOUT ");
1159 stat = USB_ST_CRC_ERR;
1160 break;
1161 }
1162 }
1163
1164 if (got_rhsc) {
1165#ifdef DEBUG
1166 ohci_dump_roothub (&gohci, 1);
1167#endif
1168 got_rhsc = 0;
1169
1170 timeout = rh_check_port_status(&gohci);
1171 if (timeout >= 0) {
1172#if 0
1173
1174 usb_hub_port_connect_change(gohci.rh.dev, timeout - 1);
1175#endif
1176
1177
1178
1179
1180
1181 devgone = dev;
1182 }
1183 }
1184
1185 dev->status = stat;
1186 dev->act_len = transfer_len;
1187
1188#ifdef DEBUG
1189 pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe));
1190#else
1191 mdelay(1);
1192#endif
1193
1194
1195 urb_free_priv (&urb_priv);
1196 return 0;
1197}
1198
1199
1200int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1201 int transfer_len)
1202{
1203 info("submit_bulk_msg");
1204 return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
1205}
1206
1207int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1208 int transfer_len, struct devrequest *setup)
1209{
1210 int maxsize = usb_maxpacket(dev, pipe);
1211
1212 info("submit_control_msg");
1213#ifdef DEBUG
1214 urb_priv.actual_length = 0;
1215 pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
1216#else
1217 mdelay(1);
1218#endif
1219 if (!maxsize) {
1220 err("submit_control_message: pipesize for pipe %lx is zero",
1221 pipe);
1222 return -1;
1223 }
1224 if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {
1225 gohci.rh.dev = dev;
1226
1227 return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,
1228 setup);
1229 }
1230
1231 return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
1232}
1233
1234int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1235 int transfer_len, int interval)
1236{
1237 info("submit_int_msg");
1238 return -1;
1239}
1240
1241
1242
1243
1244
1245
1246
1247static int hc_reset (ohci_t *ohci)
1248{
1249 int timeout = 30;
1250 int smm_timeout = 50;
1251
1252 if (readl (&ohci->regs->control) & OHCI_CTRL_IR) {
1253 writel (OHCI_OCR, &ohci->regs->cmdstatus);
1254 info("USB HC TakeOver from SMM");
1255 while (readl (&ohci->regs->control) & OHCI_CTRL_IR) {
1256 mdelay (10);
1257 if (--smm_timeout == 0) {
1258 err("USB HC TakeOver failed!");
1259 return -1;
1260 }
1261 }
1262 }
1263
1264
1265 writel (OHCI_INTR_MIE, &ohci->regs->intrdisable);
1266
1267 dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;",
1268 ohci->slot_name,
1269 readl (&ohci->regs->control));
1270
1271
1272 writel (0, &ohci->regs->control);
1273
1274
1275 writel (OHCI_HCR, &ohci->regs->cmdstatus);
1276 while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
1277 if (--timeout == 0) {
1278 err("USB HC reset timed out!");
1279 return -1;
1280 }
1281 udelay (1);
1282 }
1283 return 0;
1284}
1285
1286
1287
1288
1289
1290
1291
1292static int hc_start (ohci_t * ohci)
1293{
1294 __u32 mask;
1295 unsigned int fminterval;
1296
1297 ohci->disabled = 1;
1298
1299
1300
1301
1302 writel (0, &ohci->regs->ed_controlhead);
1303 writel (0, &ohci->regs->ed_bulkhead);
1304
1305 writel ((__u32)ohci->hcca, &ohci->regs->hcca);
1306
1307 fminterval = 0x2edf;
1308 writel ((fminterval * 9) / 10, &ohci->regs->periodicstart);
1309 fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
1310 writel (fminterval, &ohci->regs->fminterval);
1311 writel (0x628, &ohci->regs->lsthresh);
1312
1313
1314 ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
1315 ohci->disabled = 0;
1316 writel (ohci->hc_control, &ohci->regs->control);
1317
1318
1319 mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
1320 OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
1321 OHCI_INTR_OC | OHCI_INTR_MIE);
1322 writel (mask, &ohci->regs->intrdisable);
1323
1324 mask &= ~OHCI_INTR_MIE;
1325 writel (mask, &ohci->regs->intrstatus);
1326
1327 mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
1328 writel (mask, &ohci->regs->intrenable);
1329
1330#ifdef OHCI_USE_NPS
1331
1332 writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM,
1333 &ohci->regs->roothub.a);
1334 writel (RH_HS_LPSC, &ohci->regs->roothub.status);
1335#endif
1336
1337
1338 mdelay ((roothub_a (ohci) >> 23) & 0x1fe);
1339
1340
1341 ohci->rh.devnum = 0;
1342
1343 return 0;
1344}
1345
1346
1347
1348
1349
1350static int
1351hc_interrupt (void)
1352{
1353 ohci_t *ohci = &gohci;
1354 struct ohci_regs *regs = ohci->regs;
1355 int ints;
1356 int stat = -1;
1357
1358 if ((ohci->hcca->done_head != 0) && !(m32_swap (ohci->hcca->done_head) & 0x01)) {
1359 ints = OHCI_INTR_WDH;
1360 } else {
1361 ints = readl (®s->intrstatus);
1362 }
1363
1364
1365
1366 if (ints & OHCI_INTR_RHSC) {
1367 got_rhsc = 1;
1368 }
1369
1370 if (ints & OHCI_INTR_UE) {
1371 ohci->disabled++;
1372 err ("OHCI Unrecoverable Error, controller usb-%s disabled",
1373 ohci->slot_name);
1374
1375
1376#ifdef DEBUG
1377 ohci_dump (ohci, 1);
1378#else
1379 mdelay(1);
1380#endif
1381
1382
1383
1384
1385 hc_reset (ohci);
1386 return -1;
1387 }
1388
1389 if (ints & OHCI_INTR_WDH) {
1390 mdelay(1);
1391 writel (OHCI_INTR_WDH, ®s->intrdisable);
1392 stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci));
1393 writel (OHCI_INTR_WDH, ®s->intrenable);
1394 }
1395
1396 if (ints & OHCI_INTR_SO) {
1397 dbg("USB Schedule overrun\n");
1398 writel (OHCI_INTR_SO, ®s->intrenable);
1399 stat = -1;
1400 }
1401
1402
1403 if (ints & OHCI_INTR_SF) {
1404 unsigned int frame = m16_swap (ohci->hcca->frame_no) & 1;
1405 mdelay(1);
1406 writel (OHCI_INTR_SF, ®s->intrdisable);
1407 if (ohci->ed_rm_list[frame] != NULL)
1408 writel (OHCI_INTR_SF, ®s->intrenable);
1409 stat = 0xff;
1410 }
1411
1412 writel (ints, ®s->intrstatus);
1413 return stat;
1414}
1415
1416
1417
1418
1419
1420
1421
1422static void hc_release_ohci (ohci_t *ohci)
1423{
1424 dbg ("USB HC release ohci usb-%s", ohci->slot_name);
1425
1426 if (!ohci->disabled)
1427 hc_reset (ohci);
1428}
1429
1430
1431
1432#define __read_32bit_c0_register(source, sel) \
1433({ int __res; \
1434 if (sel == 0) \
1435 __asm__ __volatile__( \
1436 "mfc0\t%0, " #source "\n\t" \
1437 : "=r" (__res)); \
1438 else \
1439 __asm__ __volatile__( \
1440 ".set\tmips32\n\t" \
1441 "mfc0\t%0, " #source ", " #sel "\n\t" \
1442 ".set\tmips0\n\t" \
1443 : "=r" (__res)); \
1444 __res; \
1445})
1446
1447#define read_c0_prid() __read_32bit_c0_register($15, 0)
1448
1449
1450
1451
1452static char ohci_inited = 0;
1453
1454int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1455{
1456 u32 pin_func;
1457 u32 sys_freqctrl, sys_clksrc;
1458 u32 prid = read_c0_prid();
1459
1460 dbg("in usb_lowlevel_init\n");
1461
1462
1463 sys_freqctrl = au_readl(SYS_FREQCTRL0);
1464 sys_freqctrl &= ~0xFFF00000;
1465 au_writel(sys_freqctrl, SYS_FREQCTRL0);
1466
1467
1468 sys_clksrc = au_readl(SYS_CLKSRC);
1469 sys_clksrc &= ~0x00007FE0;
1470 au_writel(sys_clksrc, SYS_CLKSRC);
1471
1472 sys_freqctrl = au_readl(SYS_FREQCTRL0);
1473 sys_freqctrl &= ~0xFFF00000;
1474
1475 sys_clksrc = au_readl(SYS_CLKSRC);
1476 sys_clksrc &= ~0x00007FE0;
1477
1478 switch (prid & 0x000000FF) {
1479 case 0x00:
1480 case 0x01:
1481 case 0x02:
1482
1483 au_writel(4, SYS_CPUPLL);
1484
1485
1486
1487
1488
1489 sys_freqctrl |= ((3<<22) | (1<<21) | (0<<20));
1490 au_writel(sys_freqctrl, SYS_FREQCTRL0);
1491
1492
1493 au_writel(0x20, SYS_CPUPLL);
1494
1495 printf("Au1000: 48MHz OHCI workaround enabled\n");
1496 break;
1497
1498 default:
1499
1500 sys_freqctrl |= ((0<<22) | (1<<21) | (1<<20));
1501 au_writel(sys_freqctrl, SYS_FREQCTRL0);
1502 break;
1503 }
1504
1505
1506
1507
1508 sys_clksrc |= ((4<<12) | (0<<11) | (0<<10));
1509 au_writel(sys_clksrc, SYS_CLKSRC);
1510
1511
1512 pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x8080);
1513
1514 au_writel(pin_func, SYS_PINFUNC);
1515 au_writel(0x2800, SYS_TRIOUTCLR);
1516 au_writel(0x0030, SYS_OUTPUTCLR);
1517
1518 dbg("OHCI board setup complete\n");
1519
1520
1521 au_writel(USBH_ENABLE_CE, USB_HOST_CONFIG);
1522 udelay(1000);
1523 au_writel(USBH_ENABLE_INIT, USB_HOST_CONFIG);
1524 udelay(1000);
1525
1526
1527 while (au_readl(USB_HOST_CONFIG),
1528 !(au_readl(USB_HOST_CONFIG) & USBH_ENABLE_RD))
1529 udelay(1000);
1530
1531 dbg("OHCI clock running\n");
1532
1533 memset (&gohci, 0, sizeof (ohci_t));
1534 memset (&urb_priv, 0, sizeof (urb_priv_t));
1535
1536
1537 if ((__u32)&ghcca[0] & 0xff) {
1538 err("HCCA not aligned!!");
1539 return -1;
1540 }
1541 phcca = &ghcca[0];
1542 info("aligned ghcca %p", phcca);
1543 memset(&ohci_dev, 0, sizeof(struct ohci_device));
1544 if ((__u32)&ohci_dev.ed[0] & 0x7) {
1545 err("EDs not aligned!!");
1546 return -1;
1547 }
1548 memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1));
1549 if ((__u32)gtd & 0x7) {
1550 err("TDs not aligned!!");
1551 return -1;
1552 }
1553 ptd = gtd;
1554 gohci.hcca = phcca;
1555 memset (phcca, 0, sizeof (struct ohci_hcca));
1556
1557 gohci.disabled = 1;
1558 gohci.sleeping = 0;
1559 gohci.irq = -1;
1560 gohci.regs = (struct ohci_regs *)(USB_OHCI_BASE | 0xA0000000);
1561
1562 gohci.flags = 0;
1563 gohci.slot_name = "au1x00";
1564
1565 dbg("OHCI revision: 0x%08x\n"
1566 " RH: a: 0x%08x b: 0x%08x\n",
1567 readl(&gohci.regs->revision),
1568 readl(&gohci.regs->roothub.a), readl(&gohci.regs->roothub.b));
1569
1570 if (hc_reset (&gohci) < 0)
1571 goto errout;
1572
1573
1574 writel (gohci.hc_control = OHCI_USB_RESET, &gohci.regs->control);
1575 mdelay (10);
1576
1577 if (hc_start (&gohci) < 0)
1578 goto errout;
1579
1580#ifdef DEBUG
1581 ohci_dump (&gohci, 1);
1582#else
1583 mdelay(1);
1584#endif
1585 ohci_inited = 1;
1586 return 0;
1587
1588 errout:
1589 err("OHCI initialization error\n");
1590 hc_release_ohci (&gohci);
1591
1592 au_writel(readl(USB_HOST_CONFIG) & ~USBH_ENABLE_CE, USB_HOST_CONFIG);
1593 return -1;
1594}
1595
1596int usb_lowlevel_stop(int index)
1597{
1598
1599
1600 if (!ohci_inited)
1601 return 0;
1602
1603
1604 hc_reset (&gohci);
1605
1606
1607 au_writel(readl(USB_HOST_CONFIG) & ~USBH_ENABLE_CE, USB_HOST_CONFIG);
1608 return 0;
1609}
1610
1611#endif
1612