uboot/arch/powerpc/cpu/mpc8xxx/cpu.c
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   1/*
   2 * Copyright 2009-2012 Freescale Semiconductor, Inc.
   3 *
   4 * This file is derived from arch/powerpc/cpu/mpc85xx/cpu.c and
   5 * arch/powerpc/cpu/mpc86xx/cpu.c. Basically this file contains
   6 * cpu specific common code for 85xx/86xx processors.
   7 * SPDX-License-Identifier:     GPL-2.0+
   8 */
   9
  10#include <config.h>
  11#include <common.h>
  12#include <command.h>
  13#include <tsec.h>
  14#include <fm_eth.h>
  15#include <netdev.h>
  16#include <asm/cache.h>
  17#include <asm/io.h>
  18
  19DECLARE_GLOBAL_DATA_PTR;
  20
  21static struct cpu_type cpu_type_list[] = {
  22#if defined(CONFIG_MPC85xx)
  23        CPU_TYPE_ENTRY(8533, 8533, 1),
  24        CPU_TYPE_ENTRY(8535, 8535, 1),
  25        CPU_TYPE_ENTRY(8536, 8536, 1),
  26        CPU_TYPE_ENTRY(8540, 8540, 1),
  27        CPU_TYPE_ENTRY(8541, 8541, 1),
  28        CPU_TYPE_ENTRY(8543, 8543, 1),
  29        CPU_TYPE_ENTRY(8544, 8544, 1),
  30        CPU_TYPE_ENTRY(8545, 8545, 1),
  31        CPU_TYPE_ENTRY(8547, 8547, 1),
  32        CPU_TYPE_ENTRY(8548, 8548, 1),
  33        CPU_TYPE_ENTRY(8555, 8555, 1),
  34        CPU_TYPE_ENTRY(8560, 8560, 1),
  35        CPU_TYPE_ENTRY(8567, 8567, 1),
  36        CPU_TYPE_ENTRY(8568, 8568, 1),
  37        CPU_TYPE_ENTRY(8569, 8569, 1),
  38        CPU_TYPE_ENTRY(8572, 8572, 2),
  39        CPU_TYPE_ENTRY(P1010, P1010, 1),
  40        CPU_TYPE_ENTRY(P1011, P1011, 1),
  41        CPU_TYPE_ENTRY(P1012, P1012, 1),
  42        CPU_TYPE_ENTRY(P1013, P1013, 1),
  43        CPU_TYPE_ENTRY(P1014, P1014, 1),
  44        CPU_TYPE_ENTRY(P1017, P1017, 1),
  45        CPU_TYPE_ENTRY(P1020, P1020, 2),
  46        CPU_TYPE_ENTRY(P1021, P1021, 2),
  47        CPU_TYPE_ENTRY(P1022, P1022, 2),
  48        CPU_TYPE_ENTRY(P1023, P1023, 2),
  49        CPU_TYPE_ENTRY(P1024, P1024, 2),
  50        CPU_TYPE_ENTRY(P1025, P1025, 2),
  51        CPU_TYPE_ENTRY(P2010, P2010, 1),
  52        CPU_TYPE_ENTRY(P2020, P2020, 2),
  53        CPU_TYPE_ENTRY(P2040, P2040, 4),
  54        CPU_TYPE_ENTRY(P2041, P2041, 4),
  55        CPU_TYPE_ENTRY(P3041, P3041, 4),
  56        CPU_TYPE_ENTRY(P4040, P4040, 4),
  57        CPU_TYPE_ENTRY(P4080, P4080, 8),
  58        CPU_TYPE_ENTRY(P5010, P5010, 1),
  59        CPU_TYPE_ENTRY(P5020, P5020, 2),
  60        CPU_TYPE_ENTRY(P5021, P5021, 2),
  61        CPU_TYPE_ENTRY(P5040, P5040, 4),
  62        CPU_TYPE_ENTRY(T4240, T4240, 0),
  63        CPU_TYPE_ENTRY(T4120, T4120, 0),
  64        CPU_TYPE_ENTRY(T4160, T4160, 0),
  65        CPU_TYPE_ENTRY(B4860, B4860, 0),
  66        CPU_TYPE_ENTRY(G4860, G4860, 0),
  67        CPU_TYPE_ENTRY(G4060, G4060, 0),
  68        CPU_TYPE_ENTRY(B4440, B4440, 0),
  69        CPU_TYPE_ENTRY(G4440, G4440, 0),
  70        CPU_TYPE_ENTRY(B4420, B4420, 0),
  71        CPU_TYPE_ENTRY(B4220, B4220, 0),
  72        CPU_TYPE_ENTRY(T1040, T1040, 0),
  73        CPU_TYPE_ENTRY(T1041, T1041, 0),
  74        CPU_TYPE_ENTRY(T1042, T1042, 0),
  75        CPU_TYPE_ENTRY(T1020, T1020, 0),
  76        CPU_TYPE_ENTRY(T1021, T1021, 0),
  77        CPU_TYPE_ENTRY(T1022, T1022, 0),
  78        CPU_TYPE_ENTRY(T2080, T2080, 0),
  79        CPU_TYPE_ENTRY(T2081, T2081, 0),
  80        CPU_TYPE_ENTRY(BSC9130, 9130, 1),
  81        CPU_TYPE_ENTRY(BSC9131, 9131, 1),
  82        CPU_TYPE_ENTRY(BSC9132, 9132, 2),
  83        CPU_TYPE_ENTRY(BSC9232, 9232, 2),
  84        CPU_TYPE_ENTRY(C291, C291, 1),
  85        CPU_TYPE_ENTRY(C292, C292, 1),
  86        CPU_TYPE_ENTRY(C293, C293, 1),
  87#elif defined(CONFIG_MPC86xx)
  88        CPU_TYPE_ENTRY(8610, 8610, 1),
  89        CPU_TYPE_ENTRY(8641, 8641, 2),
  90        CPU_TYPE_ENTRY(8641D, 8641D, 2),
  91#endif
  92};
  93
  94#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
  95static inline u32 init_type(u32 cluster, int init_id)
  96{
  97        ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  98        u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
  99        u32 type = in_be32(&gur->tp_ityp[idx]);
 100
 101        if (type & TP_ITYP_AV)
 102                return type;
 103
 104        return 0;
 105}
 106
 107u32 compute_ppc_cpumask(void)
 108{
 109        ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 110        int i = 0, count = 0;
 111        u32 cluster, type, mask = 0;
 112
 113        do {
 114                int j;
 115                cluster = in_be32(&gur->tp_cluster[i].lower);
 116                for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 117                        type = init_type(cluster, j);
 118                        if (type) {
 119                                if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_PPC)
 120                                        mask |= 1 << count;
 121                                count++;
 122                        }
 123                }
 124                i++;
 125        } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
 126
 127        return mask;
 128}
 129
 130int fsl_qoriq_core_to_cluster(unsigned int core)
 131{
 132        ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 133        int i = 0, count = 0;
 134        u32 cluster;
 135
 136        do {
 137                int j;
 138                cluster = in_be32(&gur->tp_cluster[i].lower);
 139                for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 140                        if (init_type(cluster, j)) {
 141                                if (count == core)
 142                                        return i;
 143                                count++;
 144                        }
 145                }
 146                i++;
 147        } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
 148
 149        return -1;      /* cannot identify the cluster */
 150}
 151
 152#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
 153/*
 154 * Before chassis genenration 2, the cpumask should be hard-coded.
 155 * In case of cpu type unknown or cpumask unset, use 1 as fail save.
 156 */
 157#define compute_ppc_cpumask()   1
 158#define fsl_qoriq_core_to_cluster(x) x
 159#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
 160
 161static struct cpu_type cpu_type_unknown = CPU_TYPE_ENTRY(Unknown, Unknown, 0);
 162
 163struct cpu_type *identify_cpu(u32 ver)
 164{
 165        int i;
 166        for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) {
 167                if (cpu_type_list[i].soc_ver == ver)
 168                        return &cpu_type_list[i];
 169        }
 170        return &cpu_type_unknown;
 171}
 172
 173#define MPC8xxx_PICFRR_NCPU_MASK  0x00001f00
 174#define MPC8xxx_PICFRR_NCPU_SHIFT 8
 175
 176/*
 177 * Return a 32-bit mask indicating which cores are present on this SOC.
 178 */
 179u32 cpu_mask(void)
 180{
 181        ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
 182        struct cpu_type *cpu = gd->arch.cpu;
 183
 184        /* better to query feature reporting register than just assume 1 */
 185        if (cpu == &cpu_type_unknown)
 186        return ((in_be32(&pic->frr) & MPC8xxx_PICFRR_NCPU_MASK) >>
 187                        MPC8xxx_PICFRR_NCPU_SHIFT) + 1;
 188
 189        if (cpu->num_cores == 0)
 190                return compute_ppc_cpumask();
 191
 192        return cpu->mask;
 193}
 194
 195/*
 196 * Return the number of cores on this SOC.
 197 */
 198int cpu_numcores(void)
 199{
 200        struct cpu_type *cpu = gd->arch.cpu;
 201
 202        /*
 203         * Report # of cores in terms of the cpu_mask if we haven't
 204         * figured out how many there are yet
 205         */
 206        if (cpu->num_cores == 0)
 207                return hweight32(cpu_mask());
 208
 209        return cpu->num_cores;
 210}
 211
 212/*
 213 * Check if the given core ID is valid
 214 *
 215 * Returns zero if it isn't, 1 if it is.
 216 */
 217int is_core_valid(unsigned int core)
 218{
 219        return !!((1 << core) & cpu_mask());
 220}
 221
 222int probecpu (void)
 223{
 224        uint svr;
 225        uint ver;
 226
 227        svr = get_svr();
 228        ver = SVR_SOC_VER(svr);
 229
 230        gd->arch.cpu = identify_cpu(ver);
 231
 232        return 0;
 233}
 234
 235/* Once in memory, compute mask & # cores once and save them off */
 236int fixup_cpu(void)
 237{
 238        struct cpu_type *cpu = gd->arch.cpu;
 239
 240        if (cpu->num_cores == 0) {
 241                cpu->mask = cpu_mask();
 242                cpu->num_cores = cpu_numcores();
 243        }
 244
 245        return 0;
 246}
 247
 248/*
 249 * Initializes on-chip ethernet controllers.
 250 * to override, implement board_eth_init()
 251 */
 252int cpu_eth_init(bd_t *bis)
 253{
 254#if defined(CONFIG_ETHER_ON_FCC)
 255        fec_initialize(bis);
 256#endif
 257
 258#if defined(CONFIG_UEC_ETH)
 259        uec_standard_init(bis);
 260#endif
 261
 262#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85XX_FEC)
 263        tsec_standard_init(bis);
 264#endif
 265
 266#ifdef CONFIG_FMAN_ENET
 267        fm_standard_init(bis);
 268#endif
 269        return 0;
 270}
 271