LXR uboot/board/Marvell/db64360/mpsc.h

   1/*
   2 * (C) Copyright 2001
   3 * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 */
   7
   8/*************************************************************************
   9 * changes for Marvell DB64360 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com>
  10 *
  11  ************************************************************************/
  12
  13
  14/*
  15 * mpsc.h - header file for MPSC in uart mode (console driver)
  16 */
  17
  18#ifndef __MPSC_H__
  19#define __MPSC_H__
  20
  21/* include actual Galileo defines */
  22#include "../include/mv_gen_reg.h"
  23
  24/* driver related defines */
  25
  26int mpsc_init(int baud);
  27void mpsc_sdma_init(void);
  28void mpsc_init2(void);
  29int galbrg_set_baudrate(int channel, int rate);
  30
  31int mpsc_putchar_early(char ch);
  32char mpsc_getchar_debug(void);
  33int mpsc_test_char_debug(void);
  34
  35int mpsc_test_char_sdma(void);
  36
  37extern int (*mpsc_putchar)(char ch);
  38extern char (*mpsc_getchar)(void);
  39extern int (*mpsc_test_char)(void);
  40
  41#define CHANNEL CONFIG_MPSC_PORT
  42
  43#define TX_DESC     5
  44#define RX_DESC     20
  45
  46#define DESC_FIRST  0x00010000
  47#define DESC_LAST   0x00020000
  48#define DESC_OWNER_BIT  0x80000000
  49
  50#define TX_DEMAND   0x00800000
  51#define TX_STOP     0x00010000
  52#define RX_ENABLE   0x00000080
  53
  54#define SDMA_RX_ABORT             (1 << 15)
  55#define SDMA_TX_ABORT             (1 << 31)
  56#define MPSC_TX_ABORT             (1 << 7)
  57#define MPSC_RX_ABORT             (1 << 23)
  58#define MPSC_ENTER_HUNT           (1 << 31)
  59
  60/* MPSC defines */
  61
  62#define GALMPSC_CONNECT            0x1
  63#define GALMPSC_DISCONNECT         0x0
  64
  65#define GALMPSC_UART               0x1
  66
  67#define GALMPSC_STOP_BITS_1        0x0
  68#define GALMPSC_STOP_BITS_2        0x1
  69#define GALMPSC_CHAR_LENGTH_8      0x3
  70#define GALMPSC_CHAR_LENGTH_7      0x2
  71
  72#define GALMPSC_PARITY_ODD         0x0
  73#define GALMPSC_PARITY_EVEN        0x2
  74#define GALMPSC_PARITY_MARK        0x3
  75#define GALMPSC_PARITY_SPACE       0x1
  76#define GALMPSC_PARITY_NONE        -1
  77
  78#define GALMPSC_SERIAL_MULTIPLEX   SERIAL_PORT_MULTIPLEX           /* 0xf010 */
  79#define GALMPSC_ROUTING_REGISTER   MAIN_ROUTING_REGISTER           /* 0xb400 */
  80#define GALMPSC_RxC_ROUTE          RECEIVE_CLOCK_ROUTING_REGISTER  /* 0xb404 */
  81#define GALMPSC_TxC_ROUTE          TRANSMIT_CLOCK_ROUTING_REGISTER /* 0xb408 */
  82#define GALMPSC_MCONF_LOW          MPSC0_MAIN_CONFIGURATION_LOW    /* 0x8000 */
  83#define GALMPSC_MCONF_HIGH         MPSC0_MAIN_CONFIGURATION_HIGH   /* 0x8004 */
  84#define GALMPSC_PROTOCONF_REG      MPSC0_PROTOCOL_CONFIGURATION    /* 0x8008 */
  85
  86#define GALMPSC_REG_GAP            0x1000
  87
  88#define GALMPSC_MCONF_CHREG_BASE   CHANNEL0_REGISTER1  /* 0x800c */
  89#define GALMPSC_CHANNELREG_1       CHANNEL0_REGISTER1  /* 0x800c */
  90#define GALMPSC_CHANNELREG_2       CHANNEL0_REGISTER2  /* 0x8010 */
  91#define GALMPSC_CHANNELREG_3       CHANNEL0_REGISTER3  /* 0x8014 */
  92#define GALMPSC_CHANNELREG_4       CHANNEL0_REGISTER4  /* 0x8018 */
  93#define GALMPSC_CHANNELREG_5       CHANNEL0_REGISTER5  /* 0x801c */
  94#define GALMPSC_CHANNELREG_6       CHANNEL0_REGISTER6  /* 0x8020 */
  95#define GALMPSC_CHANNELREG_7       CHANNEL0_REGISTER7  /* 0x8024 */
  96#define GALMPSC_CHANNELREG_8       CHANNEL0_REGISTER8  /* 0x8028 */
  97#define GALMPSC_CHANNELREG_9       CHANNEL0_REGISTER9  /* 0x802c */
  98#define GALMPSC_CHANNELREG_10      CHANNEL0_REGISTER10 /* 0x8030 */
  99#define GALMPSC_CHANNELREG_11      CHANNEL0_REGISTER11 /* 0x8034 */
 100
 101#define GALSDMA_COMMAND_FIRST     (1 << 16)
 102#define GALSDMA_COMMAND_LAST      (1 << 17)
 103#define GALSDMA_COMMAND_ENABLEINT (1 << 23)
 104#define GALSDMA_COMMAND_AUTO      (1 << 30)
 105#define GALSDMA_COMMAND_OWNER     (1 << 31)
 106
 107#define GALSDMA_RX                 0
 108#define GALSDMA_TX                 1
 109
 110/* CHANNEL2 should be CHANNEL1, according to documentation,
 111 * but to work with the current GTREGS file...
 112 */
 113#define GALSDMA_0_CONF_REG         CHANNEL0_CONFIGURATION_REGISTER   /* 0x4000 */
 114#define GALSDMA_1_CONF_REG         CHANNEL2_CONFIGURATION_REGISTER   /* 0x6000 */
 115#define GALSDMA_0_COM_REG          CHANNEL0_COMMAND_REGISTER         /* 0x4008 */
 116#define GALSDMA_1_COM_REG          CHANNEL2_COMMAND_REGISTER         /* 0x6008 */
 117#define GALSDMA_0_CUR_RX_PTR       CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER  /* 0x4810 */
 118#define GALSDMA_0_CUR_TX_PTR       CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER  /* 0x4c10 */
 119#define GALSDMA_0_FIR_TX_PTR       CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER    /* 0x4c14 */
 120#define GALSDMA_1_CUR_RX_PTR       CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER  /* 0x6810 */
 121#define GALSDMA_1_CUR_TX_PTR       CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER  /* 0x6c10 */
 122#define GALSDMA_1_FIR_TX_PTR       CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER    /* 0x6c14 */
 123#define GALSDMA_REG_DIFF           0x2000
 124
 125/* WRONG in gt64260R.h */
 126#define GALSDMA_INT_CAUSE          0xb800   /* SDMA_CAUSE */
 127#define GALSDMA_INT_MASK           0xb880   /* SDMA_MASK  */
 128#define GALMPSC_0_INT_CAUSE        0xb804
 129#define GALMPSC_0_INT_MASK         0xb884
 130
 131#define GALSDMA_MODE_UART          0
 132#define GALSDMA_MODE_BISYNC        1
 133#define GALSDMA_MODE_HDLC          2
 134#define GALSDMA_MODE_TRANSPARENT   3
 135
 136#define GALBRG_0_CONFREG           BRG0_CONFIGURATION_REGISTER  /*  0xb200  */
 137#define GALBRG_REG_GAP             0x0008
 138#define GALBRG_0_BTREG             BRG0_BAUDE_TUNING_REGISTER   /*  0xb204  */
 139
 140#endif /* __MPSC_H__ */
 141