1/* 2 * (C) Copyright 2003 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * (C) Copyright 2003 6 * Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11#include <common.h> 12#include <mpc5xxx.h> 13#include <pci.h> 14 15/***************************************************************************** 16 * initialize SDRAM/DDRAM controller. 17 * TBD: get data from I2C EEPROM 18 *****************************************************************************/ 19phys_size_t initdram (int board_type) 20{ 21 ulong dramsize = 0; 22#ifndef CONFIG_SYS_RAMBOOT 23#if 0 24 ulong t; 25 ulong tap_del; 26#endif 27 28 #define MODE_EN 0x80000000 29 #define SOFT_PRE 2 30 #define SOFT_REF 4 31 32 /* configure SDRAM start/end */ 33 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = (CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | CONFIG_SYS_DRAM_RAM_SIZE; 34 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */ 35 36 /* setup config registers */ 37 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = CONFIG_SYS_DRAM_CONFIG1; 38 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = CONFIG_SYS_DRAM_CONFIG2; 39 40 /* unlock mode register */ 41 *(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL | MODE_EN; 42 /* precharge all banks */ 43 *(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL | MODE_EN | SOFT_PRE; 44#ifdef CONFIG_SYS_DRAM_DDR 45 /* set extended mode register */ 46 *(vu_short *)MPC5XXX_SDRAM_MODE = CONFIG_SYS_DRAM_EMODE; 47#endif 48 /* set mode register */ 49 *(vu_short *)MPC5XXX_SDRAM_MODE = CONFIG_SYS_DRAM_MODE | 0x0400; 50 /* precharge all banks */ 51 *(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL | MODE_EN | SOFT_PRE; 52 /* auto refresh */ 53 *(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL | MODE_EN | SOFT_REF; 54 /* set mode register */ 55 *(vu_short *)MPC5XXX_SDRAM_MODE = CONFIG_SYS_DRAM_MODE; 56 /* normal operation */ 57 *(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL; 58 /* write default TAP delay */ 59 *(vu_long *)MPC5XXX_CDM_PORCFG = CONFIG_SYS_DRAM_TAP_DEL << 24; 60 61#if 0 62 for (tap_del = 0; tap_del < 32; tap_del++) 63 { 64 *(vu_long *)MPC5XXX_CDM_PORCFG = tap_del << 24; 65 66 printf ("\nTAP Delay:%x Filling DRAM...", *(vu_long *)MPC5XXX_CDM_PORCFG); 67 for (t = 0; t < 0x04000000; t+=4) 68 *(vu_long *) t = t; 69 printf ("Checking DRAM...\n"); 70 for (t = 0; t < 0x04000000; t+=4) 71 { 72 ulong rval = *(vu_long *) t; 73 if (rval != t) 74 { 75 printf ("mismatch at %x: ", t); 76 printf (" 1.read %x", rval); 77 printf (" 2.read %x", *(vu_long *) t); 78 printf (" 3.read %x", *(vu_long *) t); 79 break; 80 } 81 } 82 } 83#endif 84#endif /* CONFIG_SYS_RAMBOOT */ 85 86 dramsize = ((1 << (*(vu_long *)MPC5XXX_SDRAM_CS0CFG - 0x13)) << 20); 87 88 /* return total ram size */ 89 return dramsize; 90} 91 92/***************************************************************************** 93 * print board identification 94 *****************************************************************************/ 95int checkboard (void) 96{ 97#if defined (CONFIG_EVAL5200) 98 puts ("Board: EMK TOP5200 on EVAL5200\n"); 99#else 100#if defined (CONFIG_LITE5200) 101 puts ("Board: LITE5200\n"); 102#else 103#if defined (CONFIG_MINI5200) 104 puts ("Board: EMK TOP5200 on MINI5200\n"); 105#else 106 puts ("Board: EMK TOP5200\n"); 107#endif 108#endif 109#endif 110 return 0; 111} 112 113/***************************************************************************** 114 * prepare for FLASH detection 115 *****************************************************************************/ 116void flash_preinit(void) 117{ 118 /* 119 * Now, when we are in RAM, enable flash write 120 * access for detection process. 121 * Note that CS_BOOT cannot be cleared when 122 * executing in flash. 123 */ 124 *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ 125} 126 127/***************************************************************************** 128 * finalize FLASH setup 129 *****************************************************************************/ 130void flash_afterinit(uint bank, ulong start, ulong size) 131{ 132 if (bank == 0) { /* adjust mapping */ 133 *(vu_long *)MPC5XXX_BOOTCS_START = 134 *(vu_long *)MPC5XXX_CS0_START = START_REG(start); 135 *(vu_long *)MPC5XXX_BOOTCS_STOP = 136 *(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(start, size); 137 } 138} 139 140/***************************************************************************** 141 * otherinits after RAM is there and we are relocated to RAM 142 * note: though this is an int function, nobody cares for the result! 143 *****************************************************************************/ 144int misc_init_r (void) 145{ 146#if !defined (CONFIG_LITE5200) 147 /* read 'factory' part of EEPROM */ 148 extern void read_factory_r (void); 149 read_factory_r (); 150#endif 151 return (0); 152} 153 154/***************************************************************************** 155 * initialize the PCI system 156 *****************************************************************************/ 157#ifdef CONFIG_PCI 158static struct pci_controller hose; 159 160extern void pci_mpc5xxx_init(struct pci_controller *); 161 162void pci_init_board(void) 163{ 164 pci_mpc5xxx_init(&hose); 165} 166#endif 167 168/***************************************************************************** 169 * provide the IDE Reset Function 170 *****************************************************************************/ 171#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) 172 173void init_ide_reset (void) 174{ 175 debug ("init_ide_reset\n"); 176 177 /* Configure PSC1_4 as GPIO output for ATA reset */ 178 *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4; 179 *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; 180} 181 182void ide_set_reset (int idereset) 183{ 184 debug ("ide_reset(%d)\n", idereset); 185 186 if (idereset) { 187 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4; 188 } else { 189 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; 190 } 191} 192#endif 193