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8#include <common.h>
9#include <asm/io.h>
10#include <asm/arch/imx-regs.h>
11#include <asm/arch/sys_proto.h>
12#include <asm/arch/crm_regs.h>
13#include <asm/arch/clock.h>
14#include <asm/arch/iomux-mx53.h>
15#include <asm/errno.h>
16#include <netdev.h>
17#include <mmc.h>
18#include <fsl_esdhc.h>
19#include <asm/gpio.h>
20
21
22#define IMA3_MX53_CS0GCR1 (CSEN | DSZ(2))
23#define IMA3_MX53_CS0GCR2 0
24#define IMA3_MX53_CS0RCR1 (RCSN(2) | OEN(1) | RWSC(15))
25#define IMA3_MX53_CS0RCR2 0
26#define IMA3_MX53_CS0WCR1 (WBED1 | WCSN(2) | WEN(1) | WWSC(15))
27#define IMA3_MX53_CS0WCR2 0
28
29DECLARE_GLOBAL_DATA_PTR;
30
31static void weim_nor_settings(void)
32{
33 struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
34
35 writel(IMA3_MX53_CS0GCR1, &weim_regs->cs0gcr1);
36 writel(IMA3_MX53_CS0GCR2, &weim_regs->cs0gcr2);
37 writel(IMA3_MX53_CS0RCR1, &weim_regs->cs0rcr1);
38 writel(IMA3_MX53_CS0RCR2, &weim_regs->cs0rcr2);
39 writel(IMA3_MX53_CS0WCR1, &weim_regs->cs0wcr1);
40 writel(IMA3_MX53_CS0WCR2, &weim_regs->cs0wcr2);
41 writel(0x0, &weim_regs->wcr);
42
43 set_chipselect_size(CS0_128);
44}
45
46int dram_init(void)
47{
48 gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
49 PHYS_SDRAM_1_SIZE);
50 return 0;
51}
52
53#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
54 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
55
56static void setup_iomux_uart(void)
57{
58 static const iomux_v3_cfg_t uart_pads[] = {
59 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT13__UART4_RXD_MUX, UART_PAD_CTRL),
60 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT12__UART4_TXD_MUX, UART_PAD_CTRL),
61 };
62
63 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
64}
65
66static void setup_iomux_fec(void)
67{
68 static const iomux_v3_cfg_t fec_pads[] = {
69 NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
70 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
71 NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
72 NEW_PAD_CTRL(MX53_PAD_KEY_COL0__FEC_RDATA_3,
73 PAD_CTL_HYS | PAD_CTL_PKE),
74 NEW_PAD_CTRL(MX53_PAD_KEY_COL2__FEC_RDATA_2,
75 PAD_CTL_HYS | PAD_CTL_PKE),
76 NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
77 PAD_CTL_HYS | PAD_CTL_PKE),
78 NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
79 PAD_CTL_HYS | PAD_CTL_PKE),
80 NEW_PAD_CTRL(MX53_PAD_GPIO_19__FEC_TDATA_3, PAD_CTL_DSE_HIGH),
81 NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__FEC_TDATA_2, PAD_CTL_DSE_HIGH),
82 NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
83 NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
84 NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
85 NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
86 PAD_CTL_HYS | PAD_CTL_PKE),
87 NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
88 PAD_CTL_HYS | PAD_CTL_PKE),
89 NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
90 PAD_CTL_HYS | PAD_CTL_PKE),
91 NEW_PAD_CTRL(MX53_PAD_KEY_COL3__FEC_CRS,
92 PAD_CTL_HYS | PAD_CTL_PKE),
93 NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__FEC_COL,
94 PAD_CTL_HYS | PAD_CTL_PKE),
95 NEW_PAD_CTRL(MX53_PAD_KEY_COL1__FEC_RX_CLK,
96 PAD_CTL_HYS | PAD_CTL_PKE),
97 };
98
99 imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
100}
101
102#ifdef CONFIG_FSL_ESDHC
103struct fsl_esdhc_cfg esdhc_cfg = { MMC_SDHC1_BASE_ADDR };
104
105int board_mmc_getcd(struct mmc *mmc)
106{
107 int ret;
108
109 ret = !gpio_get_value(IMX_GPIO_NR(1, 1));
110
111 return ret;
112}
113
114#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
115 PAD_CTL_PUS_100K_UP)
116#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
117 PAD_CTL_DSE_HIGH)
118#define SD_CD_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_HYS | PAD_CTL_PKE)
119
120int board_mmc_init(bd_t *bis)
121{
122 static const iomux_v3_cfg_t sd1_pads[] = {
123 NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
124 NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
125 NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
126 NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
127 NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
128 NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
129 NEW_PAD_CTRL(MX53_PAD_GPIO_1__GPIO1_1, SD_CD_PAD_CTRL),
130 };
131
132 imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
133 gpio_direction_input(IMX_GPIO_NR(1, 1));
134
135 esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
136 return fsl_esdhc_initialize(bis, &esdhc_cfg);
137}
138#endif
139
140#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP)
141
142static void setup_iomux_spi(void)
143{
144 static const iomux_v3_cfg_t spi_pads[] = {
145 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__ECSPI2_SCLK, SPI_PAD_CTRL),
146 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__ECSPI2_MOSI, SPI_PAD_CTRL),
147 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__ECSPI2_MISO, SPI_PAD_CTRL),
148
149 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__GPIO5_29, SPI_PAD_CTRL),
150 };
151
152 imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
153 gpio_direction_output(IMX_GPIO_NR(5, 29), 1);
154}
155
156int board_early_init_f(void)
157{
158
159 setup_iomux_uart();
160 setup_iomux_fec();
161
162 weim_nor_settings();
163
164
165 setup_iomux_spi();
166
167 return 0;
168}
169
170int board_init(void)
171{
172 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
173
174 mxc_set_sata_internal_clock();
175
176 return 0;
177}
178
179#if defined(CONFIG_RESET_PHY_R)
180#include <miiphy.h>
181
182void reset_phy(void)
183{
184 unsigned short reg;
185
186
187 miiphy_reset("FEC", CONFIG_PHY_ADDR);
188
189
190 miiphy_read("FEC", CONFIG_PHY_ADDR, MII_BMCR, ®);
191 reg &= ~BMCR_ANENABLE;
192 reg |= (BMCR_SPEED100 | BMCR_FULLDPLX);
193 miiphy_write("FEC", CONFIG_PHY_ADDR, MII_BMCR, reg);
194
195 miiphy_read("FEC", CONFIG_PHY_ADDR, 0x16, ®);
196 reg |= (1 << 5);
197 miiphy_write("FEC", CONFIG_PHY_ADDR, 0x16, reg);
198}
199#endif
200
201int checkboard(void)
202{
203 puts("Board: IMA3_MX53\n");
204
205 return 0;
206}
207
