LXR uboot/board/gateworks/gw_ventana/gw

   1/*
   2 * Copyright (C) 2013 Gateworks Corporation
   3 *
   4 * Author: Tim Harvey <tharvey@gateworks.com>
   5 *
   6 * SPDX-License-Identifier: GPL-2.0+
   7 */
   8
   9#include <common.h>
  10#include <asm/io.h>
  11#include <asm/arch/clock.h>
  12#include <asm/arch/imx-regs.h>
  13#include <asm/arch/iomux.h>
  14#include <asm/arch/mx6-pins.h>
  15#include <asm/arch/crm_regs.h>
  16#include <asm/arch/sys_proto.h>
  17#include <asm/gpio.h>
  18#include <asm/imx-common/iomux-v3.h>
  19#include <asm/imx-common/mxc_i2c.h>
  20#include <asm/imx-common/boot_mode.h>
  21#include <asm/imx-common/sata.h>
  22#include <jffs2/load_kernel.h>
  23#include <hwconfig.h>
  24#include <i2c.h>
  25#include <linux/ctype.h>
  26#include <fdt_support.h>
  27#include <fsl_esdhc.h>
  28#include <miiphy.h>
  29#include <mmc.h>
  30#include <mtd_node.h>
  31#include <netdev.h>
  32#include <power/pmic.h>
  33#include <power/pfuze100_pmic.h>
  34#include <i2c.h>
  35#include <fdt_support.h>
  36#include <jffs2/load_kernel.h>
  37#include <spi_flash.h>
  38
  39#include "gsc.h"
  40#include "ventana_eeprom.h"
  41
  42DECLARE_GLOBAL_DATA_PTR;
  43
  44/* GPIO's common to all baseboards */
  45#define GP_PHY_RST      IMX_GPIO_NR(1, 30)
  46#define GP_USB_OTG_PWR  IMX_GPIO_NR(3, 22)
  47#define GP_SD3_CD       IMX_GPIO_NR(7, 0)
  48#define GP_RS232_EN     IMX_GPIO_NR(2, 11)
  49#define GP_MSATA_SEL    IMX_GPIO_NR(2, 8)
  50
  51/* I2C bus numbers */
  52#define I2C_GSC         0
  53#define I2C_PMIC        1
  54
  55#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  56        PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  57        PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  58
  59#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
  60        PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |               \
  61        PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  62
  63#define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  64        PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
  65        PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
  66
  67#define SPI_PAD_CTRL (PAD_CTL_HYS |                             \
  68        PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED |             \
  69        PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
  70
  71#define DIO_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |              \
  72        PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  73        PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
  74
  75#define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                    \
  76        PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  77        PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  78
  79/*
  80 * EEPROM board info struct populated by read_eeprom so that we only have to
  81 * read it once.
  82 */
  83static struct ventana_board_info ventana_info;
  84
  85enum {
  86        GW54proto, /* original GW5400-A prototype */
  87        GW51xx,
  88        GW52xx,
  89        GW53xx,
  90        GW54xx,
  91        GW_UNKNOWN,
  92};
  93
  94int board_type;
  95
  96/* UART1: Function varies per baseboard */
  97iomux_v3_cfg_t const uart1_pads[] = {
  98        MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  99        MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 100};
 101
 102/* UART2: Serial Console */
 103iomux_v3_cfg_t const uart2_pads[] = {
 104        MX6_PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 105        MX6_PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 106};
 107
 108#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 109
 110/* I2C1: GSC */
 111struct i2c_pads_info i2c_pad_info0 = {
 112        .scl = {
 113                .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
 114                .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC,
 115                .gp = IMX_GPIO_NR(3, 21)
 116        },
 117        .sda = {
 118                .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
 119                .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC,
 120                .gp = IMX_GPIO_NR(3, 28)
 121        }
 122};
 123
 124/* I2C2: PMIC/PCIe Switch/PCIe Clock/Mezz */
 125struct i2c_pads_info i2c_pad_info1 = {
 126        .scl = {
 127                .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
 128                .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
 129                .gp = IMX_GPIO_NR(4, 12)
 130        },
 131        .sda = {
 132                .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
 133                .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 134                .gp = IMX_GPIO_NR(4, 13)
 135        }
 136};
 137
 138/* I2C3: Misc/Expansion */
 139struct i2c_pads_info i2c_pad_info2 = {
 140        .scl = {
 141                .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
 142                .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
 143                .gp = IMX_GPIO_NR(1, 3)
 144        },
 145        .sda = {
 146                .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC,
 147                .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC,
 148                .gp = IMX_GPIO_NR(1, 6)
 149        }
 150};
 151
 152/* MMC */
 153iomux_v3_cfg_t const usdhc3_pads[] = {
 154        MX6_PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 155        MX6_PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 156        MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 157        MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 158        MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 159        MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 160        MX6_PAD_SD3_DAT5__GPIO7_IO00  | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 161};
 162
 163/* ENET */
 164iomux_v3_cfg_t const enet_pads[] = {
 165        MX6_PAD_ENET_MDIO__ENET_MDIO            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 166        MX6_PAD_ENET_MDC__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
 167        MX6_PAD_RGMII_TXC__RGMII_TXC            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 168        MX6_PAD_RGMII_TD0__RGMII_TD0            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 169        MX6_PAD_RGMII_TD1__RGMII_TD1            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 170        MX6_PAD_RGMII_TD2__RGMII_TD2            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 171        MX6_PAD_RGMII_TD3__RGMII_TD3            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 172        MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 173        MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 174        MX6_PAD_RGMII_RXC__RGMII_RXC            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 175        MX6_PAD_RGMII_RD0__RGMII_RD0            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 176        MX6_PAD_RGMII_RD1__RGMII_RD1            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 177        MX6_PAD_RGMII_RD2__RGMII_RD2            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 178        MX6_PAD_RGMII_RD3__RGMII_RD3            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 179        MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 180        /* PHY nRST */
 181        MX6_PAD_ENET_TXD0__GPIO1_IO30           | MUX_PAD_CTRL(NO_PAD_CTRL),
 182};
 183
 184/* NAND */
 185iomux_v3_cfg_t const nfc_pads[] = {
 186        MX6_PAD_NANDF_CLE__NAND_CLE     | MUX_PAD_CTRL(NO_PAD_CTRL),
 187        MX6_PAD_NANDF_ALE__NAND_ALE     | MUX_PAD_CTRL(NO_PAD_CTRL),
 188        MX6_PAD_NANDF_WP_B__NAND_WP_B   | MUX_PAD_CTRL(NO_PAD_CTRL),
 189        MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
 190        MX6_PAD_NANDF_CS0__NAND_CE0_B   | MUX_PAD_CTRL(NO_PAD_CTRL),
 191        MX6_PAD_SD4_CMD__NAND_RE_B      | MUX_PAD_CTRL(NO_PAD_CTRL),
 192        MX6_PAD_SD4_CLK__NAND_WE_B      | MUX_PAD_CTRL(NO_PAD_CTRL),
 193        MX6_PAD_NANDF_D0__NAND_DATA00   | MUX_PAD_CTRL(NO_PAD_CTRL),
 194        MX6_PAD_NANDF_D1__NAND_DATA01   | MUX_PAD_CTRL(NO_PAD_CTRL),
 195        MX6_PAD_NANDF_D2__NAND_DATA02   | MUX_PAD_CTRL(NO_PAD_CTRL),
 196        MX6_PAD_NANDF_D3__NAND_DATA03   | MUX_PAD_CTRL(NO_PAD_CTRL),
 197        MX6_PAD_NANDF_D4__NAND_DATA04   | MUX_PAD_CTRL(NO_PAD_CTRL),
 198        MX6_PAD_NANDF_D5__NAND_DATA05   | MUX_PAD_CTRL(NO_PAD_CTRL),
 199        MX6_PAD_NANDF_D6__NAND_DATA06   | MUX_PAD_CTRL(NO_PAD_CTRL),
 200        MX6_PAD_NANDF_D7__NAND_DATA07   | MUX_PAD_CTRL(NO_PAD_CTRL),
 201};
 202
 203#ifdef CONFIG_CMD_NAND
 204static void setup_gpmi_nand(void)
 205{
 206        struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 207
 208        /* config gpmi nand iomux */
 209        imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
 210
 211        /* config gpmi and bch clock to 100 MHz */
 212        clrsetbits_le32(&mxc_ccm->cs2cdr,
 213                        MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
 214                        MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
 215                        MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
 216                        MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
 217                        MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
 218                        MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
 219
 220        /* enable gpmi and bch clock gating */
 221        setbits_le32(&mxc_ccm->CCGR4,
 222                     MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 223                     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 224                     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 225                     MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 226                     MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
 227
 228        /* enable apbh clock gating */
 229        setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
 230}
 231#endif
 232
 233static void setup_iomux_enet(void)
 234{
 235        imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 236
 237        /* toggle PHY_RST# */
 238        gpio_direction_output(GP_PHY_RST, 0);
 239        mdelay(2);
 240        gpio_set_value(GP_PHY_RST, 1);
 241}
 242
 243static void setup_iomux_uart(void)
 244{
 245        imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 246        imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
 247}
 248
 249#ifdef CONFIG_USB_EHCI_MX6
 250iomux_v3_cfg_t const usb_pads[] = {
 251        MX6_PAD_GPIO_1__USB_OTG_ID   | MUX_PAD_CTRL(DIO_PAD_CTRL),
 252        MX6_PAD_KEY_COL4__USB_OTG_OC | MUX_PAD_CTRL(DIO_PAD_CTRL),
 253        MX6_PAD_EIM_D22__GPIO3_IO22  | MUX_PAD_CTRL(DIO_PAD_CTRL), /* OTG PWR */
 254};
 255
 256int board_ehci_hcd_init(int port)
 257{
 258        struct ventana_board_info *info = &ventana_info;
 259
 260        imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
 261
 262        /* Reset USB HUB (present on GW54xx/GW53xx) */
 263        switch (info->model[3]) {
 264        case '3': /* GW53xx */
 265                imx_iomux_v3_setup_pad(MX6_PAD_GPIO_9__GPIO1_IO09|
 266                                       MUX_PAD_CTRL(NO_PAD_CTRL));
 267                gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
 268                mdelay(2);
 269                gpio_set_value(IMX_GPIO_NR(1, 9), 1);
 270                break;
 271        case '4': /* GW54xx */
 272                imx_iomux_v3_setup_pad(MX6_PAD_SD1_DAT0__GPIO1_IO16 |
 273                                       MUX_PAD_CTRL(NO_PAD_CTRL));
 274                gpio_direction_output(IMX_GPIO_NR(1, 16), 0);
 275                mdelay(2);
 276                gpio_set_value(IMX_GPIO_NR(1, 16), 1);
 277                break;
 278        }
 279
 280        return 0;
 281}
 282
 283int board_ehci_power(int port, int on)
 284{
 285        if (port)
 286                return 0;
 287        gpio_set_value(GP_USB_OTG_PWR, on);
 288        return 0;
 289}
 290#endif /* CONFIG_USB_EHCI_MX6 */
 291
 292#ifdef CONFIG_FSL_ESDHC
 293struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
 294
 295int board_mmc_getcd(struct mmc *mmc)
 296{
 297        /* Card Detect */
 298        gpio_direction_input(GP_SD3_CD);
 299        return !gpio_get_value(GP_SD3_CD);
 300}
 301
 302int board_mmc_init(bd_t *bis)
 303{
 304        /* Only one USDHC controller on Ventana */
 305        imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 306        usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 307        usdhc_cfg.max_bus_width = 4;
 308
 309        return fsl_esdhc_initialize(bis, &usdhc_cfg);
 310}
 311#endif /* CONFIG_FSL_ESDHC */
 312
 313#ifdef CONFIG_MXC_SPI
 314iomux_v3_cfg_t const ecspi1_pads[] = {
 315        /* SS1 */
 316        MX6_PAD_EIM_D19__GPIO3_IO19  | MUX_PAD_CTRL(SPI_PAD_CTRL),
 317        MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 318        MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
 319        MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
 320};
 321
 322static void setup_spi(void)
 323{
 324        gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1);
 325        imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
 326                                         ARRAY_SIZE(ecspi1_pads));
 327}
 328#endif
 329
 330/* configure eth0 PHY board-specific LED behavior */
 331int board_phy_config(struct phy_device *phydev)
 332{
 333        unsigned short val;
 334
 335        /* Marvel 88E1510 */
 336        if (phydev->phy_id == 0x1410dd1) {
 337                /*
 338                 * Page 3, Register 16: LED[2:0] Function Control Register
 339                 * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
 340                 * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
 341                 */
 342                phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
 343                val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
 344                val &= 0xff00;
 345                val |= 0x0017;
 346                phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
 347                phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
 348        }
 349
 350        if (phydev->drv->config)
 351                phydev->drv->config(phydev);
 352
 353        return 0;
 354}
 355
 356int board_eth_init(bd_t *bis)
 357{
 358        setup_iomux_enet();
 359
 360#ifdef CONFIG_FEC_MXC
 361        cpu_eth_init(bis);
 362#endif
 363
 364#ifdef CONFIG_CI_UDC
 365        /* For otg ethernet*/
 366        usb_eth_initialize(bis);
 367#endif
 368
 369        return 0;
 370}
 371
 372/* read ventana EEPROM, check for validity, and return baseboard type */
 373static int
 374read_eeprom(void)
 375{
 376        int i;
 377        int chksum;
 378        char baseboard;
 379        int type;
 380        struct ventana_board_info *info = &ventana_info;
 381        unsigned char *buf = (unsigned char *)&ventana_info;
 382
 383        memset(info, 0, sizeof(ventana_info));
 384
 385        /*
 386         * On a board with a missing/depleted backup battery for GSC, the
 387         * board may be ready to probe the GSC before its firmware is
 388         * running.  We will wait here indefinately for the GSC/EEPROM.
 389         */
 390        while (1) {
 391                if (0 == i2c_set_bus_num(I2C_GSC) &&
 392                    0 == i2c_probe(GSC_EEPROM_ADDR))
 393                        break;
 394                mdelay(1);
 395        }
 396
 397        /* read eeprom config section */
 398        if (gsc_i2c_read(GSC_EEPROM_ADDR, 0x00, 1, buf, sizeof(ventana_info))) {
 399                puts("EEPROM: Failed to read EEPROM\n");
 400                info->model[0] = 0;
 401                return GW_UNKNOWN;
 402        }
 403
 404        /* sanity checks */
 405        if (info->model[0] != 'G' || info->model[1] != 'W') {
 406                puts("EEPROM: Invalid Model in EEPROM\n");
 407                info->model[0] = 0;
 408                return GW_UNKNOWN;
 409        }
 410
 411        /* validate checksum */
 412        for (chksum = 0, i = 0; i < sizeof(*info)-2; i++)
 413                chksum += buf[i];
 414        if ((info->chksum[0] != chksum>>8) ||
 415            (info->chksum[1] != (chksum&0xff))) {
 416                puts("EEPROM: Failed EEPROM checksum\n");
 417                info->model[0] = 0;
 418                return GW_UNKNOWN;
 419        }
 420
 421        /* original GW5400-A prototype */
 422        baseboard = info->model[3];
 423        if (strncasecmp((const char *)info->model, "GW5400-A", 8) == 0)
 424                baseboard = '0';
 425
 426        switch (baseboard) {
 427        case '0': /* original GW5400-A prototype */
 428                type = GW54proto;
 429                break;
 430        case '1':
 431                type = GW51xx;
 432                break;
 433        case '2':
 434                type = GW52xx;
 435                break;
 436        case '3':
 437                type = GW53xx;
 438                break;
 439        case '4':
 440                type = GW54xx;
 441                break;
 442        default:
 443                printf("EEPROM: Unknown model in EEPROM: %s\n", info->model);
 444                type = GW_UNKNOWN;
 445                break;
 446        }
 447        return type;
 448}
 449
 450/*
 451 * Baseboard specific GPIO
 452 */
 453
 454/* common to add baseboards */
 455static iomux_v3_cfg_t const gw_gpio_pads[] = {
 456        /* MSATA_EN */
 457        MX6_PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
 458        /* RS232_EN# */
 459        MX6_PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
 460};
 461
 462/* prototype */
 463static iomux_v3_cfg_t const gwproto_gpio_pads[] = {
 464        /* PANLEDG# */
 465        MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
 466        /* PANLEDR# */
 467        MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
 468        /* LOCLED# */
 469        MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
 470        /* RS485_EN */
 471        MX6_PAD_SD3_DAT4__GPIO7_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL),
 472        /* IOEXP_PWREN# */
 473        MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
 474        /* IOEXP_IRQ# */
 475        MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
 476        /* VID_EN */
 477        MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
 478        /* DIOI2C_DIS# */
 479        MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
 480        /* PCICK_SSON */
 481        MX6_PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
 482        /* PCI_RST# */
 483        MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
 484};
 485
 486static iomux_v3_cfg_t const gw51xx_gpio_pads[] = {
 487        /* PANLEDG# */
 488        MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
 489        /* PANLEDR# */
 490        MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
 491        /* IOEXP_PWREN# */
 492        MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
 493        /* IOEXP_IRQ# */
 494        MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
 495
 496        /* GPS_SHDN */
 497        MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
 498        /* VID_PWR */
 499        MX6_PAD_CSI0_DATA_EN__GPIO5_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
 500        /* PCI_RST# */
 501        MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
 502};
 503
 504static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {
 505        /* PANLEDG# */
 506        MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
 507        /* PANLEDR# */
 508        MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
 509        /* IOEXP_PWREN# */
 510        MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
 511        /* IOEXP_IRQ# */
 512        MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
 513
 514        /* MX6_LOCLED# */
 515        MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
 516        /* GPS_SHDN */
 517        MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
 518        /* USBOTG_SEL */
 519        MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
 520        /* VID_PWR */
 521        MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
 522        /* PCI_RST# */
 523        MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
 524};
 525
 526static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
 527        /* PANLEDG# */
 528        MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
 529        /* PANLEDR# */
 530        MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
 531        /* IOEXP_PWREN# */
 532        MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
 533        /* IOEXP_IRQ# */
 534        MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
 535
 536        /* MX6_LOCLED# */
 537        MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
 538        /* GPS_SHDN */
 539        MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
 540        /* VID_EN */
 541        MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
 542        /* PCI_RST# */
 543        MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
 544};
 545
 546static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {
 547        /* PANLEDG# */
 548        MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
 549        /* PANLEDR# */
 550        MX6_PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
 551        /* MX6_LOCLED# */
 552        MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
 553        /* MIPI_DIO */
 554        MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
 555        /* RS485_EN */
 556        MX6_PAD_EIM_D24__GPIO3_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
 557        /* IOEXP_PWREN# */
 558        MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
 559        /* IOEXP_IRQ# */
 560        MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
 561        /* DIOI2C_DIS# */
 562        MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
 563        /* DIOI2C_DIS# */
 564        MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
 565        /* PCICK_SSON */
 566        MX6_PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
 567        /* PCI_RST# */
 568        MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
 569};
 570
 571/*
 572 * each baseboard has 4 user configurable Digital IO lines which can
 573 * be pinmuxed as a GPIO or in some cases a PWM
 574 */
 575struct dio_cfg {
 576        iomux_v3_cfg_t gpio_padmux;
 577        unsigned gpio_param;
 578        iomux_v3_cfg_t pwm_padmux;
 579        unsigned pwm_param;
 580};
 581
 582struct ventana {
 583        /* pinmux */
 584        iomux_v3_cfg_t const *gpio_pads;
 585        int num_pads;
 586        /* DIO pinmux/val */
 587        struct dio_cfg dio_cfg[4];
 588        /* various gpios (0 if non-existent) */
 589        int leds[3];
 590        int pcie_rst;
 591        int mezz_pwren;
 592        int mezz_irq;
 593        int rs485en;
 594        int gps_shdn;
 595        int vidin_en;
 596        int dioi2c_en;
 597        int pcie_sson;
 598        int usb_sel;
 599};
 600
 601struct ventana gpio_cfg[] = {
 602        /* GW5400proto */
 603        {
 604                .gpio_pads = gw54xx_gpio_pads,
 605                .num_pads = ARRAY_SIZE(gw54xx_gpio_pads),
 606                .dio_cfg = {
 607                        { MX6_PAD_GPIO_9__GPIO1_IO09, IMX_GPIO_NR(1, 9),
 608                          MX6_PAD_GPIO_9__PWM1_OUT, 1 },
 609                        { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19),
 610                          MX6_PAD_SD1_DAT2__PWM2_OUT, 2 },
 611                        { MX6_PAD_SD4_DAT1__GPIO2_IO09, IMX_GPIO_NR(2, 9),
 612                          MX6_PAD_SD4_DAT1__PWM3_OUT, 3 },
 613                        { MX6_PAD_SD4_DAT2__GPIO2_IO10, IMX_GPIO_NR(2, 10),
 614                          MX6_PAD_SD4_DAT2__PWM4_OUT, 4 },
 615                },
 616                .leds = {
 617                        IMX_GPIO_NR(4, 6),
 618                        IMX_GPIO_NR(4, 10),
 619                        IMX_GPIO_NR(4, 15),
 620                },
 621                .pcie_rst = IMX_GPIO_NR(1, 29),
 622                .mezz_pwren = IMX_GPIO_NR(4, 7),
 623                .mezz_irq = IMX_GPIO_NR(4, 9),
 624                .rs485en = IMX_GPIO_NR(3, 24),
 625                .dioi2c_en = IMX_GPIO_NR(4,  5),
 626                .pcie_sson = IMX_GPIO_NR(1, 20),
 627        },
 628
 629        /* GW51xx */
 630        {
 631                .gpio_pads = gw51xx_gpio_pads,
 632                .num_pads = ARRAY_SIZE(gw51xx_gpio_pads),
 633                .dio_cfg = {
 634                        { MX6_PAD_SD1_DAT0__GPIO1_IO16, IMX_GPIO_NR(1, 16),
 635                          0, 0 },
 636                        { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19),
 637                          MX6_PAD_SD1_DAT2__PWM2_OUT, 2 },
 638                        { MX6_PAD_SD1_DAT1__GPIO1_IO17, IMX_GPIO_NR(1, 17),
 639                          MX6_PAD_SD1_DAT1__PWM3_OUT, 3 },
 640                        { MX6_PAD_SD1_CMD__GPIO1_IO18, IMX_GPIO_NR(1, 18),
 641                          MX6_PAD_SD1_CMD__PWM4_OUT, 4 },
 642                },
 643                .leds = {
 644                        IMX_GPIO_NR(4, 6),
 645                        IMX_GPIO_NR(4, 10),
 646                },
 647                .pcie_rst = IMX_GPIO_NR(1, 0),
 648                .mezz_pwren = IMX_GPIO_NR(2, 19),
 649                .mezz_irq = IMX_GPIO_NR(2, 18),
 650                .gps_shdn = IMX_GPIO_NR(1, 2),
 651                .vidin_en = IMX_GPIO_NR(5, 20),
 652        },
 653
 654        /* GW52xx */
 655        {
 656                .gpio_pads = gw52xx_gpio_pads,
 657                .num_pads = ARRAY_SIZE(gw52xx_gpio_pads),
 658                .dio_cfg = {
 659                        { MX6_PAD_SD1_DAT0__GPIO1_IO16, IMX_GPIO_NR(1, 16),
 660                          0, 0 },
 661                        { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19),
 662                          MX6_PAD_SD1_DAT2__PWM2_OUT, 2 },
 663                        { MX6_PAD_SD1_DAT1__GPIO1_IO17, IMX_GPIO_NR(1, 17),
 664                          MX6_PAD_SD1_DAT1__PWM3_OUT, 3 },
 665                        { MX6_PAD_SD1_CLK__GPIO1_IO20, IMX_GPIO_NR(1, 20),
 666                          0, 0 },
 667                },
 668                .leds = {
 669                        IMX_GPIO_NR(4, 6),
 670                        IMX_GPIO_NR(4, 7),
 671                        IMX_GPIO_NR(4, 15),
 672                },
 673                .pcie_rst = IMX_GPIO_NR(1, 29),
 674                .mezz_pwren = IMX_GPIO_NR(2, 19),
 675                .mezz_irq = IMX_GPIO_NR(2, 18),
 676                .gps_shdn = IMX_GPIO_NR(1, 27),
 677                .vidin_en = IMX_GPIO_NR(3, 31),
 678                .usb_sel = IMX_GPIO_NR(1, 2),
 679        },
 680
 681        /* GW53xx */
 682        {
 683                .gpio_pads = gw53xx_gpio_pads,
 684                .num_pads = ARRAY_SIZE(gw53xx_gpio_pads),
 685                .dio_cfg = {
 686                        { MX6_PAD_SD1_DAT0__GPIO1_IO16, IMX_GPIO_NR(1, 16),
 687                          0, 0 },
 688                        { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19),
 689                          MX6_PAD_SD1_DAT2__PWM2_OUT, 2 },
 690                        { MX6_PAD_SD1_DAT1__GPIO1_IO17, IMX_GPIO_NR(1, 17),
 691                          MX6_PAD_SD1_DAT1__PWM3_OUT, 3 },
 692                        { MX6_PAD_SD1_CLK__GPIO1_IO20, IMX_GPIO_NR(1, 20),
 693                          0, 0 },
 694                },
 695                .leds = {
 696                        IMX_GPIO_NR(4, 6),
 697                        IMX_GPIO_NR(4, 7),
 698                        IMX_GPIO_NR(4, 15),
 699                },
 700                .pcie_rst = IMX_GPIO_NR(1, 29),
 701                .mezz_pwren = IMX_GPIO_NR(2, 19),
 702                .mezz_irq = IMX_GPIO_NR(2, 18),
 703                .gps_shdn = IMX_GPIO_NR(1, 27),
 704                .vidin_en = IMX_GPIO_NR(3, 31),
 705        },
 706
 707        /* GW54xx */
 708        {
 709                .gpio_pads = gw54xx_gpio_pads,
 710                .num_pads = ARRAY_SIZE(gw54xx_gpio_pads),
 711                .dio_cfg = {
 712                        { MX6_PAD_GPIO_9__GPIO1_IO09, IMX_GPIO_NR(1, 9),
 713                          MX6_PAD_GPIO_9__PWM1_OUT, 1 },
 714                        { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19),
 715                          MX6_PAD_SD1_DAT2__PWM2_OUT, 2 },
 716                        { MX6_PAD_SD4_DAT1__GPIO2_IO09, IMX_GPIO_NR(2, 9),
 717                          MX6_PAD_SD4_DAT1__PWM3_OUT, 3 },
 718                        { MX6_PAD_SD4_DAT2__GPIO2_IO10, IMX_GPIO_NR(2, 10),
 719                          MX6_PAD_SD4_DAT2__PWM4_OUT, 4 },
 720                },
 721                .leds = {
 722                        IMX_GPIO_NR(4, 6),
 723                        IMX_GPIO_NR(4, 7),
 724                        IMX_GPIO_NR(4, 15),
 725                },
 726                .pcie_rst = IMX_GPIO_NR(1, 29),
 727                .mezz_pwren = IMX_GPIO_NR(2, 19),
 728                .mezz_irq = IMX_GPIO_NR(2, 18),
 729                .rs485en = IMX_GPIO_NR(7, 1),
 730                .vidin_en = IMX_GPIO_NR(3, 31),
 731                .dioi2c_en = IMX_GPIO_NR(4,  5),
 732                .pcie_sson = IMX_GPIO_NR(1, 20),
 733        },
 734};
 735
 736/* setup GPIO pinmux and default configuration per baseboard */
 737static void setup_board_gpio(int board)
 738{
 739        struct ventana_board_info *info = &ventana_info;
 740        const char *s;
 741        char arg[10];
 742        size_t len;
 743        int i;
 744        int quiet = simple_strtol(getenv("quiet"), NULL, 10);
 745
 746        if (board >= GW_UNKNOWN)
 747                return;
 748
 749        /* RS232_EN# */
 750        gpio_direction_output(GP_RS232_EN, (hwconfig("rs232")) ? 0 : 1);
 751
 752        /* MSATA Enable */
 753        if (is_cpu_type(MXC_CPU_MX6Q) &&
 754            test_bit(EECONFIG_SATA, info->config)) {
 755                gpio_direction_output(GP_MSATA_SEL,
 756                                      (hwconfig("msata")) ?  1 : 0);
 757        } else {
 758                gpio_direction_output(GP_MSATA_SEL, 0);
 759        }
 760
 761        /*
 762         * assert PCI_RST# (released by OS when clock is valid)
 763         * TODO: figure out why leaving this de-asserted from PCI scan on boot
 764         *       causes linux pcie driver to hang during enumeration
 765         */
 766        gpio_direction_output(gpio_cfg[board].pcie_rst, 0);
 767
 768        /* turn off (active-high) user LED's */
 769        for (i = 0; i < 4; i++) {
 770                if (gpio_cfg[board].leds[i])
 771                        gpio_direction_output(gpio_cfg[board].leds[i], 1);
 772        }
 773
 774        /* Expansion Mezzanine IO */
 775        gpio_direction_output(gpio_cfg[board].mezz_pwren, 0);
 776        gpio_direction_input(gpio_cfg[board].mezz_irq);
 777
 778        /* RS485 Transmit Enable */
 779        if (gpio_cfg[board].rs485en)
 780                gpio_direction_output(gpio_cfg[board].rs485en, 0);
 781
 782        /* GPS_SHDN */
 783        if (gpio_cfg[board].gps_shdn)
 784                gpio_direction_output(gpio_cfg[board].gps_shdn, 1);
 785
 786        /* Analog video codec power enable */
 787        if (gpio_cfg[board].vidin_en)
 788                gpio_direction_output(gpio_cfg[board].vidin_en, 1);
 789
 790        /* DIOI2C_DIS# */
 791        if (gpio_cfg[board].dioi2c_en)
 792                gpio_direction_output(gpio_cfg[board].dioi2c_en, 0);
 793
 794        /* PCICK_SSON: disable spread-spectrum clock */
 795        if (gpio_cfg[board].pcie_sson)
 796                gpio_direction_output(gpio_cfg[board].pcie_sson, 0);
 797
 798        /* USBOTG Select (PCISKT or FrontPanel) */
 799        if (gpio_cfg[board].usb_sel)
 800                gpio_direction_output(gpio_cfg[board].usb_sel, 0);
 801
 802        /*
 803         * Configure DIO pinmux/padctl registers
 804         * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions
 805         */
 806        for (i = 0; i < 4; i++) {
 807                struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i];
 808                unsigned ctrl = DIO_PAD_CTRL;
 809
 810                sprintf(arg, "dio%d", i);
 811                if (!hwconfig(arg))
 812                        continue;
 813                s = hwconfig_subarg(arg, "padctrl", &len);
 814                if (s)
 815                        ctrl = simple_strtoul(s, NULL, 16) & 0x3ffff;
 816                if (hwconfig_subarg_cmp(arg, "mode", "gpio")) {
 817                        if (!quiet) {
 818                                printf("DIO%d:  GPIO%d_IO%02d (gpio-%d)\n", i,
 819                                       (cfg->gpio_param/32)+1,
 820                                       cfg->gpio_param%32,
 821                                       cfg->gpio_param);
 822                        }
 823                        imx_iomux_v3_setup_pad(cfg->gpio_padmux |
 824                                               MUX_PAD_CTRL(ctrl));
 825                        gpio_direction_input(cfg->gpio_param);
 826                } else if (hwconfig_subarg_cmp("dio2", "mode", "pwm") &&
 827                           cfg->pwm_padmux) {
 828                        if (!quiet)
 829                                printf("DIO%d:  pwm%d\n", i, cfg->pwm_param);
 830                        imx_iomux_v3_setup_pad(cfg->pwm_padmux |
 831                                               MUX_PAD_CTRL(ctrl));
 832                }
 833        }
 834
 835        if (!quiet) {
 836                if (is_cpu_type(MXC_CPU_MX6Q) &&
 837                    (test_bit(EECONFIG_SATA, info->config))) {
 838                        printf("MSATA: %s\n", (hwconfig("msata") ?
 839                               "enabled" : "disabled"));
 840                }
 841                printf("RS232: %s\n", (hwconfig("rs232")) ?
 842                       "enabled" : "disabled");
 843        }
 844}
 845
 846#if defined(CONFIG_CMD_PCI)
 847int imx6_pcie_toggle_reset(void)
 848{
 849        if (board_type < GW_UNKNOWN) {
 850                gpio_direction_output(gpio_cfg[board_type].pcie_rst, 0);
 851                mdelay(50);
 852                gpio_direction_output(gpio_cfg[board_type].pcie_rst, 1);
 853        }
 854        return 0;
 855}
 856#endif /* CONFIG_CMD_PCI */
 857
 858#ifdef CONFIG_SERIAL_TAG
 859/*
 860 * called when setting up ATAGS before booting kernel
 861 * populate serialnum from the following (in order of priority):
 862 *   serial# env var
 863 *   eeprom
 864 */
 865void get_board_serial(struct tag_serialnr *serialnr)
 866{
 867        char *serial = getenv("serial#");
 868
 869        if (serial) {
 870                serialnr->high = 0;
 871                serialnr->low = simple_strtoul(serial, NULL, 10);
 872        } else if (ventana_info.model[0]) {
 873                serialnr->high = 0;
 874                serialnr->low = ventana_info.serial;
 875        } else {
 876                serialnr->high = 0;
 877                serialnr->low = 0;
 878        }
 879}
 880#endif
 881
 882/*
 883 * Board Support
 884 */
 885
 886int board_early_init_f(void)
 887{
 888        setup_iomux_uart();
 889        gpio_direction_output(GP_USB_OTG_PWR, 0); /* OTG power off */
 890
 891        return 0;
 892}
 893
 894int dram_init(void)
 895{
 896        gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
 897                                    CONFIG_DDR_MB*1024*1024);
 898
 899        return 0;
 900}
 901
 902int board_init(void)
 903{
 904        struct iomuxc_base_regs *const iomuxc_regs
 905                = (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
 906
 907        clrsetbits_le32(&iomuxc_regs->gpr[1],
 908                        IOMUXC_GPR1_OTG_ID_MASK,
 909                        IOMUXC_GPR1_OTG_ID_GPIO1);
 910
 911        /* address of linux boot parameters */
 912        gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 913
 914#ifdef CONFIG_CMD_NAND
 915        setup_gpmi_nand();
 916#endif
 917#ifdef CONFIG_MXC_SPI
 918        setup_spi();
 919#endif
 920        setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
 921        setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 922        setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 923
 924#ifdef CONFIG_CMD_SATA
 925        setup_sata();
 926#endif
 927        /* read Gateworks EEPROM into global struct (used later) */
 928        board_type = read_eeprom();
 929
 930        /* board-specifc GPIO iomux */
 931        if (board_type < GW_UNKNOWN) {
 932                imx_iomux_v3_setup_multiple_pads(gw_gpio_pads,
 933                                                 ARRAY_SIZE(gw_gpio_pads));
 934                imx_iomux_v3_setup_multiple_pads(gpio_cfg[board_type].gpio_pads,
 935                                                 gpio_cfg[board_type].num_pads);
 936        }
 937
 938        return 0;
 939}
 940
 941#if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
 942/*
 943 * called during late init (after relocation and after board_init())
 944 * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and
 945 * EEPROM read.
 946 */
 947int checkboard(void)
 948{
 949        struct ventana_board_info *info = &ventana_info;
 950        unsigned char buf[4];
 951        const char *p;
 952        int quiet; /* Quiet or minimal output mode */
 953
 954        quiet = 0;
 955        p = getenv("quiet");
 956        if (p)
 957                quiet = simple_strtol(p, NULL, 10);
 958        else
 959                setenv("quiet", "0");
 960
 961        puts("\nGateworks Corporation Copyright 2014\n");
 962        if (info->model[0]) {
 963                printf("Model: %s\n", info->model);
 964                printf("MFGDate: %02x-%02x-%02x%02x\n",
 965                       info->mfgdate[0], info->mfgdate[1],
 966                       info->mfgdate[2], info->mfgdate[3]);
 967                printf("Serial:%d\n", info->serial);
 968        } else {
 969                puts("Invalid EEPROM - board will not function fully\n");
 970        }
 971        if (quiet)
 972                return 0;
 973
 974        /* Display GSC firmware revision/CRC/status */
 975        i2c_set_bus_num(I2C_GSC);
 976        if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_FWVER, 1, buf, 1)) {
 977                printf("GSC:   v%d", buf[0]);
 978                if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, buf, 4)) {
 979                        printf(" 0x%04x", buf[2] | buf[3]<<8); /* CRC */
 980                        printf(" 0x%02x", buf[0]); /* irq status */
 981                }
 982                puts("\n");
 983        }
 984        /* Display RTC */
 985        if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) {
 986                printf("RTC:   %d\n",
 987                       buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24);
 988        }
 989
 990        return 0;
 991}
 992#endif
 993
 994#ifdef CONFIG_CMD_BMODE
 995/*
 996 * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
 997 * see Table 8-11 and Table 5-9
 998 *  BOOT_CFG1[7] = 1 (boot from NAND)
 999 *  BOOT_CFG1[5] = 0 - raw NAND
1000 *  BOOT_CFG1[4] = 0 - default pad settings

1001 *  BOOT_CFG1[3:2] = 00 - devices = 1
1002 *  BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
1003 *  BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
1004 *  BOOT_CFG2[2:1] = 01 - Pages In Block = 64
1005 *  BOOT_CFG2[0] = 0 - Reset time 12ms
1006 */
1007static const struct boot_mode board_boot_modes[] = {
1008        /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
1009        { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
1010        { NULL, 0 },
1011};
1012#endif
1013
1014/* late init */
1015int misc_init_r(void)
1016{
1017        struct ventana_board_info *info = &ventana_info;
1018        unsigned char reg;
1019
1020        /* set env vars based on EEPROM data */
1021        if (ventana_info.model[0]) {
1022                char str[16], fdt[36];
1023                char *p;
1024                const char *cputype = "";
1025                int i;
1026
1027                /*
1028                 * FDT name will be prefixed with CPU type.  Three versions
1029                 * will be created each increasingly generic and bootloader
1030                 * env scripts will try loading each from most specific to
1031                 * least.
1032                 */
1033                if (is_cpu_type(MXC_CPU_MX6Q))
1034                        cputype = "imx6q";
1035                else if (is_cpu_type(MXC_CPU_MX6DL))
1036                        cputype = "imx6dl";
1037                memset(str, 0, sizeof(str));
1038                for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
1039                        str[i] = tolower(info->model[i]);
1040                if (!getenv("model"))
1041                        setenv("model", str);
1042                if (!getenv("fdt_file")) {
1043                        sprintf(fdt, "%s-%s.dtb", cputype, str);
1044                        setenv("fdt_file", fdt);
1045                }
1046                p = strchr(str, '-');
1047                if (p) {
1048                        *p++ = 0;
1049
1050                        setenv("model_base", str);
1051                        if (!getenv("fdt_file1")) {
1052                                sprintf(fdt, "%s-%s.dtb", cputype, str);
1053                                setenv("fdt_file1", fdt);
1054                        }
1055                        str[4] = 'x';
1056                        str[5] = 'x';
1057                        str[6] = 0;
1058                        if (!getenv("fdt_file2")) {
1059                                sprintf(fdt, "%s-%s.dtb", cputype, str);
1060                                setenv("fdt_file2", fdt);
1061                        }
1062                }
1063
1064                /* initialize env from EEPROM */
1065                if (test_bit(EECONFIG_ETH0, info->config) &&
1066                    !getenv("ethaddr")) {
1067                        eth_setenv_enetaddr("ethaddr", info->mac0);
1068                }
1069                if (test_bit(EECONFIG_ETH1, info->config) &&
1070                    !getenv("eth1addr")) {
1071                        eth_setenv_enetaddr("eth1addr", info->mac1);
1072                }
1073
1074                /* board serial-number */
1075                sprintf(str, "%6d", info->serial);
1076                setenv("serial#", str);
1077        }
1078
1079        /* configure PFUZE100 PMIC (not used on all Ventana baseboards) */
1080        if ((board_type == GW54xx || board_type == GW54proto) &&
1081            !pmic_init(I2C_PMIC)) {
1082                struct pmic *p = pmic_get("PFUZE100_PMIC");
1083                u32 reg;
1084                if (p && !pmic_probe(p)) {
1085                        pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
1086                        printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
1087
1088                        /* Set VGEN1 to 1.5V and enable */
1089                        pmic_reg_read(p, PFUZE100_VGEN1VOL, &reg);
1090                        reg &= ~(LDO_VOL_MASK);
1091                        reg |= (LDOA_1_50V | LDO_EN);
1092                        pmic_reg_write(p, PFUZE100_VGEN1VOL, reg);
1093
1094                        /* Set SWBST to 5.0V and enable */
1095                        pmic_reg_read(p, PFUZE100_SWBSTCON1, &reg);
1096                        reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK);
1097                        reg |= (SWBST_5_00V | SWBST_MODE_AUTO);
1098                        pmic_reg_write(p, PFUZE100_SWBSTCON1, reg);
1099                }
1100        }
1101
1102        /* setup baseboard specific GPIO pinmux and config */
1103        setup_board_gpio(board_type);
1104
1105#ifdef CONFIG_CMD_BMODE
1106        add_board_boot_modes(board_boot_modes);
1107#endif
1108
1109        /*
1110         *  The Gateworks System Controller implements a boot
1111         *  watchdog (always enabled) as a workaround for IMX6 boot related
1112         *  errata such as:
1113         *    ERR005768 - no fix
1114         *    ERR006282 - fixed in silicon r1.3
1115         *    ERR007117 - fixed in silicon r1.3
1116         *    ERR007220 - fixed in silicon r1.3
1117         *  see http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf
1118         *
1119         * Disable the boot watchdog and display/clear the timeout flag if set
1120         */
1121        i2c_set_bus_num(I2C_GSC);
1122        if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1)) {
1123                reg |= (1 << GSC_SC_CTRL1_WDDIS);
1124                if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1))
1125                        puts("Error: could not disable GSC Watchdog\n");
1126        } else {
1127                puts("Error: could not disable GSC Watchdog\n");
1128        }
1129        if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, &reg, 1)) {
1130                if (reg & (1 << GSC_SC_IRQ_WATCHDOG)) { /* watchdog timeout */
1131                        puts("GSC boot watchdog timeout detected");
1132                        reg &= ~(1 << GSC_SC_IRQ_WATCHDOG); /* clear flag */
1133                        gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, 1, &reg, 1);
1134                }
1135        }
1136
1137        return 0;
1138}
1139
1140#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
1141
1142/* FDT aliases associated with EEPROM config bits */
1143const char *fdt_aliases[] = {
1144        "ethernet0",
1145        "ethernet1",
1146        "hdmi_out",
1147        "ahci0",
1148        "pcie",
1149        "ssi0",
1150        "ssi1",
1151        "lcd0",
1152        "lvds0",
1153        "lvds1",
1154        "usb0",
1155        "usb1",
1156        "mmc0",
1157        "mmc1",
1158        "mmc2",
1159        "mmc3",
1160        "uart0",
1161        "uart1",
1162        "uart2",
1163        "uart3",
1164        "uart4",
1165        "ipu0",
1166        "ipu1",
1167        "can0",
1168        "mipi_dsi",
1169        "mipi_csi",
1170        "tzasc0",
1171        "tzasc1",
1172        "i2c0",
1173        "i2c1",
1174        "i2c2",
1175        "vpu",
1176        "csi0",
1177        "csi1",
1178        "caam",
1179        NULL,
1180        NULL,
1181        NULL,
1182        NULL,
1183        NULL,
1184        "spi0",
1185        "spi1",
1186        "spi2",
1187        "spi3",
1188        "spi4",
1189        "spi5",
1190        NULL,
1191        NULL,
1192        "pps",
1193        NULL,
1194        NULL,
1195        NULL,
1196        "hdmi_in",
1197        "cvbs_out",
1198        "cvbs_in",
1199        "nand",
1200        NULL,
1201        NULL,
1202        NULL,
1203        NULL,
1204        NULL,
1205        NULL,
1206        NULL,
1207        NULL,
1208};
1209
1210/*
1211 * called prior to booting kernel or by 'fdt boardsetup' command
1212 *
1213 * unless 'fdt_noauto' env var is set we will update the following in the DTB:
1214 *  - mtd partitions based on mtdparts/mtdids env
1215 *  - system-serial (board serial num from EEPROM)
1216 *  - board (full model from EEPROM)
1217 *  - peripherals removed from DTB if not loaded on board (per EEPROM config)
1218 */
1219void ft_board_setup(void *blob, bd_t *bd)
1220{
1221        int bit;
1222        struct ventana_board_info *info = &ventana_info;
1223        struct node_info nodes[] = {
1224                { "sst,w25q256",          MTD_DEV_TYPE_NOR, },  /* SPI flash */
1225                { "fsl,imx6q-gpmi-nand",  MTD_DEV_TYPE_NAND, }, /* NAND flash */
1226        };
1227        const char *model = getenv("model");
1228
1229        if (getenv("fdt_noauto")) {
1230                puts("   Skiping ft_board_setup (fdt_noauto defined)\n");
1231                return;
1232        }
1233
1234        /* Update partition nodes using info from mtdparts env var */
1235        puts("   Updating MTD partitions...\n");
1236        fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1237
1238        if (!model) {
1239                puts("invalid board info: Leaving FDT fully enabled\n");
1240                return;
1241        }
1242        printf("   Adjusting FDT per EEPROM for %s...\n", model);
1243
1244        /* board serial number */
1245        fdt_setprop(blob, 0, "system-serial", getenv("serial#"),
1246                    strlen(getenv("serial#") + 1));
1247
1248        /* board (model contains model from device-tree) */
1249        fdt_setprop(blob, 0, "board", info->model,
1250                    strlen((const char *)info->model) + 1);
1251
1252        /*
1253         * Peripheral Config:
1254         *  remove nodes by alias path if EEPROM config tells us the
1255         *  peripheral is not loaded on the board.
1256         */
1257        for (bit = 0; bit < 64; bit++) {
1258                if (!test_bit(bit, info->config))
1259                        fdt_del_node_and_alias(blob, fdt_aliases[bit]);
1260        }
1261}
1262#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */
1263
1264