LXR uboot/board/prodrive/p3mx/pci.c

   1/*
   2 * (C) Copyright 2000
   3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 */
   7/* PCI.c - PCI functions */
   8
   9
  10#include <common.h>
  11#ifdef CONFIG_PCI
  12#include <pci.h>
  13
  14#include "../../Marvell/include/pci.h"
  15
  16#undef DEBUG
  17#undef IDE_SET_NATIVE_MODE
  18static unsigned int local_buses[] = { 0, 0 };
  19
  20static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = {
  21        {0, 0, 0, 0, 0, 0, 0, 27, 27, [9 ... PCI_MAX_DEVICES - 1] = 0 },
  22        {0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES - 1] = 0 },
  23};
  24
  25#ifdef CONFIG_USE_CPCIDVI
  26typedef struct {
  27        unsigned int base;
  28        unsigned int init;
  29} GT_CPCIDVI_ROM_T;
  30
  31static GT_CPCIDVI_ROM_T gt_cpcidvi_rom = {0, 0};
  32#endif
  33
  34#ifdef DEBUG
  35static const unsigned int pci_bus_list[] = { PCI_0_MODE, PCI_1_MODE };
  36static void gt_pci_bus_mode_display (PCI_HOST host)
  37{
  38        unsigned int mode;
  39
  40
  41        mode = (GTREGREAD (pci_bus_list[host]) & (BIT4 | BIT5)) >> 4;
  42        switch (mode) {
  43        case 0:
  44                printf ("PCI %d bus mode: Conventional PCI\n", host);
  45                break;
  46        case 1:
  47                printf ("PCI %d bus mode: 66 MHz PCIX\n", host);
  48                break;
  49        case 2:
  50                printf ("PCI %d bus mode: 100 MHz PCIX\n", host);
  51                break;
  52        case 3:
  53                printf ("PCI %d bus mode: 133 MHz PCIX\n", host);
  54                break;
  55        default:
  56                printf ("Unknown BUS %d\n", mode);
  57        }
  58}
  59#endif
  60
  61static const unsigned int pci_p2p_configuration_reg[] = {
  62        PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
  63};
  64
  65static const unsigned int pci_configuration_address[] = {
  66        PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS
  67};
  68
  69static const unsigned int pci_configuration_data[] = {
  70        PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
  71        PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER
  72};
  73
  74static const unsigned int pci_error_cause_reg[] = {
  75        PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE
  76};
  77
  78static const unsigned int pci_arbiter_control[] = {
  79        PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL
  80};
  81
  82static const unsigned int pci_address_space_en[] = {
  83        PCI_0_BASE_ADDR_REG_ENABLE, PCI_1_BASE_ADDR_REG_ENABLE
  84};
  85
  86static const unsigned int pci_snoop_control_base_0_low[] = {
  87        PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW
  88};
  89static const unsigned int pci_snoop_control_top_0[] = {
  90        PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0
  91};
  92
  93static const unsigned int pci_access_control_base_0_low[] = {
  94        PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW
  95};
  96static const unsigned int pci_access_control_top_0[] = {
  97        PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0
  98};
  99
 100static const unsigned int pci_scs_bank_size[2][4] = {
 101        {PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE,
 102         PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE},
 103        {PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE,
 104         PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE}
 105};
 106
 107static const unsigned int pci_p2p_configuration[] = {
 108        PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
 109};
 110
 111
 112/********************************************************************
 113* pciWriteConfigReg - Write to a PCI configuration register
 114*                   - Make sure the GT is configured as a master before writing
 115*                     to another device on the PCI.
 116*                   - The function takes care of Big/Little endian conversion.
 117*
 118*
 119* Inputs:   unsigned int regOffset: The register offset as it apears in the GT spec
 120*                  (or any other PCI device spec)
 121*           pciDevNum: The device number needs to be addressed.
 122*
 123*  Configuration Address 0xCF8:
 124*
 125*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
 126*  |congif|Reserved|  Bus |Device|Function|Register|00|
 127*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
 128*
 129*********************************************************************/
 130void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset,
 131                        unsigned int pciDevNum, unsigned int data)
 132{
 133        volatile unsigned int DataForAddrReg;
 134        unsigned int functionNum;
 135        unsigned int busNum = 0;
 136        unsigned int addr;
 137
 138        if (pciDevNum > 32)     /* illegal device Number */
 139                return;
 140        if (pciDevNum == SELF) {        /* configure our configuration space. */
 141                pciDevNum =
 142                        (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
 143                        0x1f;
 144                busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
 145                        0xff0000;
 146        }
 147        functionNum = regOffset & 0x00000700;
 148        pciDevNum = pciDevNum << 11;
 149        regOffset = regOffset & 0xfc;
 150        DataForAddrReg =
 151                (regOffset | pciDevNum | functionNum | busNum) | BIT31;
 152        GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
 153        GT_REG_READ (pci_configuration_address[host], &addr);
 154        if (addr != DataForAddrReg)
 155                return;
 156        GT_REG_WRITE (pci_configuration_data[host], data);
 157}
 158
 159/********************************************************************
 160* pciReadConfigReg  - Read from a PCI0 configuration register
 161*                   - Make sure the GT is configured as a master before reading
 162*                     from another device on the PCI.
 163*                   - The function takes care of Big/Little endian conversion.
 164* INPUTS:   regOffset: The register offset as it apears in the GT spec (or PCI
 165*                       spec)
 166*           pciDevNum: The device number needs to be addressed.
 167* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
 168*                 cause register to make sure the data is valid
 169*
 170*  Configuration Address 0xCF8:
 171*
 172*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
 173*  |congif|Reserved|  Bus |Device|Function|Register|00|
 174*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
 175*
 176*********************************************************************/
 177unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
 178                               unsigned int pciDevNum)
 179{
 180        volatile unsigned int DataForAddrReg;
 181        unsigned int data;
 182        unsigned int functionNum;
 183        unsigned int busNum = 0;
 184
 185        if (pciDevNum > 32)     /* illegal device Number */
 186                return 0xffffffff;
 187        if (pciDevNum == SELF) {        /* configure our configuration space. */
 188                pciDevNum =
 189                        (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
 190                        0x1f;
 191                busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
 192                        0xff0000;
 193        }
 194        functionNum = regOffset & 0x00000700;
 195        pciDevNum = pciDevNum << 11;
 196        regOffset = regOffset & 0xfc;
 197        DataForAddrReg =
 198                (regOffset | pciDevNum | functionNum | busNum) | BIT31;
 199        GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
 200        GT_REG_READ (pci_configuration_address[host], &data);
 201        if (data != DataForAddrReg)
 202                return 0xffffffff;
 203        GT_REG_READ (pci_configuration_data[host], &data);
 204        return data;
 205}
 206
 207/********************************************************************
 208* pciOverBridgeWriteConfigReg - Write to a PCI configuration register where
 209*                               the agent is placed on another Bus. For more
 210*                               information read P2P in the PCI spec.
 211*
 212* Inputs:   unsigned int regOffset - The register offset as it apears in the
 213*           GT spec (or any other PCI device spec).
 214*           unsigned int pciDevNum - The device number needs to be addressed.
 215*           unsigned int busNum - On which bus does the Target agent connect
 216*                                 to.
 217*           unsigned int data - data to be written.
 218*
 219*  Configuration Address 0xCF8:
 220*
 221*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
 222*  |congif|Reserved|  Bus |Device|Function|Register|01|
 223*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
 224*
 225*  The configuration Address is configure as type-I (bits[1:0] = '01') due to
 226*   PCI spec referring to P2P.
 227*
 228*********************************************************************/
 229void pciOverBridgeWriteConfigReg (PCI_HOST host,
 230                                  unsigned int regOffset,
 231                                  unsigned int pciDevNum,
 232                                  unsigned int busNum, unsigned int data)
 233{
 234        unsigned int DataForReg;
 235        unsigned int functionNum;
 236
 237        functionNum = regOffset & 0x00000700;
 238        pciDevNum = pciDevNum << 11;
 239        regOffset = regOffset & 0xff;
 240        busNum = busNum << 16;
 241        if (pciDevNum == SELF) {        /* This board */
 242                DataForReg = (regOffset | pciDevNum | functionNum) | BIT0;
 243        } else {
 244                DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
 245                        BIT31 | BIT0;
 246        }
 247        GT_REG_WRITE (pci_configuration_address[host], DataForReg);
 248        GT_REG_WRITE (pci_configuration_data[host], data);
 249}
 250
 251
 252/********************************************************************
 253* pciOverBridgeReadConfigReg  - Read from a PCIn configuration register where
 254*                               the agent target locate on another PCI bus.
 255*                             - Make sure the GT is configured as a master
 256*                               before reading from another device on the PCI.
 257*                             - The function takes care of Big/Little endian
 258*                               conversion.
 259* INPUTS:   regOffset: The register offset as it apears in the GT spec (or PCI
 260*                        spec). (configuration register offset.)
 261*           pciDevNum: The device number needs to be addressed.
 262*           busNum: the Bus number where the agent is place.
 263* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
 264*                 cause register to make sure the data is valid
 265*
 266*  Configuration Address 0xCF8:
 267*
 268*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
 269*  |congif|Reserved|  Bus |Device|Function|Register|01|
 270*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
 271*
 272*********************************************************************/
 273unsigned int pciOverBridgeReadConfigReg (PCI_HOST host,
 274                                         unsigned int regOffset,
 275                                         unsigned int pciDevNum,
 276                                         unsigned int busNum)
 277{
 278        unsigned int DataForReg;
 279        unsigned int data;
 280        unsigned int functionNum;
 281
 282        functionNum = regOffset & 0x00000700;
 283        pciDevNum = pciDevNum << 11;
 284        regOffset = regOffset & 0xff;
 285        busNum = busNum << 16;
 286        if (pciDevNum == SELF) {        /* This board */
 287                DataForReg = (regOffset | pciDevNum | functionNum) | BIT31;
 288        } else {                /* agent on another bus */
 289
 290                DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
 291                        BIT0 | BIT31;
 292        }
 293        GT_REG_WRITE (pci_configuration_address[host], DataForReg);
 294        GT_REG_READ (pci_configuration_data[host], &data);
 295        return data;
 296}
 297
 298
 299/********************************************************************
 300* pciGetRegOffset - Gets the register offset for this region config.
 301*
 302* INPUT:   Bus, Region - The bus and region we ask for its base address.
 303* OUTPUT:   N/A
 304* RETURNS: PCI register base address
 305*********************************************************************/
 306static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region)
 307{
 308        switch (host) {
 309        case PCI_HOST0:
 310                switch (region) {
 311                case PCI_IO:
 312                        return PCI_0I_O_LOW_DECODE_ADDRESS;
 313                case PCI_REGION0:
 314                        return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
 315                case PCI_REGION1:
 316                        return PCI_0MEMORY1_LOW_DECODE_ADDRESS;
 317                case PCI_REGION2:
 318                        return PCI_0MEMORY2_LOW_DECODE_ADDRESS;
 319                case PCI_REGION3:
 320                        return PCI_0MEMORY3_LOW_DECODE_ADDRESS;
 321                }
 322        case PCI_HOST1:
 323                switch (region) {
 324                case PCI_IO:
 325                        return PCI_1I_O_LOW_DECODE_ADDRESS;
 326                case PCI_REGION0:
 327                        return PCI_1MEMORY0_LOW_DECODE_ADDRESS;
 328                case PCI_REGION1:
 329                        return PCI_1MEMORY1_LOW_DECODE_ADDRESS;
 330                case PCI_REGION2:
 331                        return PCI_1MEMORY2_LOW_DECODE_ADDRESS;
 332                case PCI_REGION3:
 333                        return PCI_1MEMORY3_LOW_DECODE_ADDRESS;
 334                }
 335        }
 336        return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
 337}
 338
 339static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region)
 340{
 341        switch (host) {
 342        case PCI_HOST0:
 343                switch (region) {
 344                case PCI_IO:
 345                        return PCI_0I_O_ADDRESS_REMAP;
 346                case PCI_REGION0:
 347                        return PCI_0MEMORY0_ADDRESS_REMAP;
 348                case PCI_REGION1:
 349                        return PCI_0MEMORY1_ADDRESS_REMAP;
 350                case PCI_REGION2:
 351                        return PCI_0MEMORY2_ADDRESS_REMAP;
 352                case PCI_REGION3:
 353                        return PCI_0MEMORY3_ADDRESS_REMAP;
 354                }
 355        case PCI_HOST1:
 356                switch (region) {
 357                case PCI_IO:
 358                        return PCI_1I_O_ADDRESS_REMAP;
 359                case PCI_REGION0:
 360                        return PCI_1MEMORY0_ADDRESS_REMAP;
 361                case PCI_REGION1:
 362                        return PCI_1MEMORY1_ADDRESS_REMAP;
 363                case PCI_REGION2:
 364                        return PCI_1MEMORY2_ADDRESS_REMAP;
 365                case PCI_REGION3:
 366                        return PCI_1MEMORY3_ADDRESS_REMAP;
 367                }
 368        }
 369        return PCI_0MEMORY0_ADDRESS_REMAP;
 370}
 371
 372/********************************************************************
 373* pciGetBaseAddress - Gets the base address of a PCI.
 374*           - If the PCI size is 0 then this base address has no meaning!!!
 375*
 376*
 377* INPUT:   Bus, Region - The bus and region we ask for its base address.
 378* OUTPUT:   N/A
 379* RETURNS: PCI base address.
 380*********************************************************************/
 381unsigned int pciGetBaseAddress (PCI_HOST host, PCI_REGION region)
 382{
 383        unsigned int regBase;
 384        unsigned int regEnd;
 385        unsigned int regOffset = pciGetRegOffset (host, region);
 386
 387        GT_REG_READ (regOffset, &regBase);
 388        GT_REG_READ (regOffset + 8, &regEnd);
 389
 390        if (regEnd <= regBase)
 391                return 0xffffffff;      /* ERROR !!! */
 392
 393        regBase = regBase << 16;
 394        return regBase;
 395}
 396
 397bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase,
 398                  unsigned int bankBase, unsigned int bankLength)
 399{
 400        unsigned int low = 0xfff;
 401        unsigned int high = 0x0;
 402        unsigned int regOffset = pciGetRegOffset (host, region);
 403        unsigned int remapOffset = pciGetRemapOffset (host, region);
 404
 405        if (bankLength != 0) {
 406                low = (bankBase >> 16) & 0xffff;
 407                high = ((bankBase + bankLength) >> 16) - 1;
 408        }
 409
 410        GT_REG_WRITE (regOffset, low | (1 << 24));      /* no swapping */
 411        GT_REG_WRITE (regOffset + 8, high);
 412
 413        if (bankLength != 0) {  /* must do AFTER writing maps */
 414                GT_REG_WRITE (remapOffset, remapBase >> 16);    /* sorry, 32 bits only.
 415                                                                   dont support upper 32
 416                                                                   in this driver */
 417        }
 418        return true;
 419}
 420
 421unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region)
 422{
 423        unsigned int low;
 424        unsigned int regOffset = pciGetRegOffset (host, region);
 425
 426        GT_REG_READ (regOffset, &low);
 427        return (low & 0xffff) << 16;
 428}
 429
 430unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region)
 431{
 432        unsigned int low, high;
 433        unsigned int regOffset = pciGetRegOffset (host, region);
 434
 435        GT_REG_READ (regOffset, &low);
 436        GT_REG_READ (regOffset + 8, &high);
 437        return ((high & 0xffff) + 1) << 16;
 438}
 439
 440
 441/* ronen - 7/Dec/03*/
 442/********************************************************************
 443* gtPciDisable/EnableInternalBAR - This function enable/disable PCI BARS.
 444* Inputs: one of the PCI BAR
 445*********************************************************************/
 446void gtPciEnableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
 447{
 448        RESET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
 449}
 450
 451void gtPciDisableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
 452{
 453        SET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
 454}
 455
 456/********************************************************************
 457* pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave.
 458*
 459* Inputs: base and size of PCI SCS
 460*********************************************************************/
 461void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank,
 462                       unsigned int pciDramBase, unsigned int pciDramSize)
 463{
 464        /*ronen different function for 3rd bank. */
 465        unsigned int offset = (bank < 2) ? bank * 8 : 0x100 + (bank - 2) * 8;
 466
 467        pciDramBase = pciDramBase & 0xfffff000;
 468        pciDramBase = pciDramBase | (pciReadConfigReg (host,
 469                                                       PCI_SCS_0_BASE_ADDRESS
 470                                                       + offset,
 471                                                       SELF) & 0x00000fff);
 472        pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + offset, SELF,
 473                           pciDramBase);
 474        if (pciDramSize == 0)
 475                pciDramSize++;
 476        GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1);
 477        gtPciEnableInternalBAR (host, bank);
 478}
 479
 480/********************************************************************
 481* pciSetRegionFeatures - This function modifys one of the 8 regions with
 482*                         feature bits given as an input.
 483*                       - Be advised to check the spec before modifying them.
 484* Inputs: PCI_PROTECT_REGION region - one of the eight regions.
 485*         unsigned int features - See file: pci.h there are defintion for those
 486*                                 region features.
 487*         unsigned int baseAddress - The region base Address.
 488*         unsigned int topAddress - The region top Address.
 489* Returns: false if one of the parameters is erroneous true otherwise.
 490*********************************************************************/
 491bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region,
 492                           unsigned int features, unsigned int baseAddress,
 493                           unsigned int regionLength)
 494{
 495        unsigned int accessLow;
 496        unsigned int accessHigh;
 497        unsigned int accessTop = baseAddress + regionLength;
 498
 499        if (regionLength == 0) {        /* close the region. */
 500                pciDisableAccessRegion (host, region);
 501                return true;
 502        }
 503        /* base Address is store is bits [11:0] */
 504        accessLow = (baseAddress & 0xfff00000) >> 20;
 505        /* All the features are update according to the defines in pci.h (to be on
 506           the safe side we disable bits: [11:0] */
 507        accessLow = accessLow | (features & 0xfffff000);
 508        /* write to the Low Access Region register */
 509        GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
 510                      accessLow);
 511
 512        accessHigh = (accessTop & 0xfff00000) >> 20;
 513
 514        /* write to the High Access Region register */
 515        GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region,
 516                      accessHigh - 1);
 517        return true;
 518}
 519
 520/********************************************************************
 521* pciDisableAccessRegion - Disable The given Region by writing MAX size
 522*                           to its low Address and MIN size to its high Address.
 523*
 524* Inputs:   PCI_ACCESS_REGIONS region - The region we to be Disabled.
 525* Returns:  N/A.
 526*********************************************************************/
 527void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region)
 528{
 529        /* writing back the registers default values. */
 530        GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
 531                      0x01001fff);
 532        GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0);
 533}
 534
 535/********************************************************************
 536* pciArbiterEnable - Enables PCI-0`s Arbitration mechanism.
 537*
 538* Inputs:   N/A
 539* Returns:  true.
 540*********************************************************************/
 541bool pciArbiterEnable (PCI_HOST host)
 542{
 543        unsigned int regData;
 544
 545        GT_REG_READ (pci_arbiter_control[host], &regData);
 546        GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31);
 547        return true;
 548}
 549
 550/********************************************************************
 551* pciArbiterDisable - Disable PCI-0`s Arbitration mechanism.
 552*
 553* Inputs:   N/A
 554* Returns:  true
 555*********************************************************************/
 556bool pciArbiterDisable (PCI_HOST host)
 557{
 558        unsigned int regData;
 559
 560        GT_REG_READ (pci_arbiter_control[host], &regData);
 561        GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff);
 562        return true;
 563}
 564
 565/********************************************************************
 566* pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low)
 567*
 568* Inputs:   PCI_AGENT_PRIO internalAgent - priotity for internal agent.
 569*           PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent.
 570*           PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent.
 571*           PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent.
 572*           PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent.
 573*           PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent.
 574*           PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent.
 575* Returns:  true
 576*********************************************************************/
 577bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent,
 578                                  PCI_AGENT_PRIO externalAgent0,
 579                                  PCI_AGENT_PRIO externalAgent1,
 580                                  PCI_AGENT_PRIO externalAgent2,
 581                                  PCI_AGENT_PRIO externalAgent3,
 582                                  PCI_AGENT_PRIO externalAgent4,
 583                                  PCI_AGENT_PRIO externalAgent5)
 584{
 585        unsigned int regData;
 586        unsigned int writeData;
 587
 588        GT_REG_READ (pci_arbiter_control[host], &regData);
 589        writeData = (internalAgent << 7) + (externalAgent0 << 8) +
 590                (externalAgent1 << 9) + (externalAgent2 << 10) +
 591                (externalAgent3 << 11) + (externalAgent4 << 12) +
 592                (externalAgent5 << 13);
 593        regData = (regData & 0xffffc07f) | writeData;
 594        GT_REG_WRITE (pci_arbiter_control[host], regData & regData);
 595        return true;
 596}
 597
 598/********************************************************************
 599* pciParkingDisable - Park on last option disable, with this function you can
 600*                      disable the park on last mechanism for each agent.
 601*                      disabling this option for all agents results parking
 602*                      on the internal master.
 603*
 604* Inputs: PCI_AGENT_PARK internalAgent -  parking Disable for internal agent.
 605*         PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent.
 606*         PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent.
 607*         PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent.
 608*         PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent.
 609*         PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent.
 610*         PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent.
 611* Returns:  true
 612*********************************************************************/
 613bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent,
 614                        PCI_AGENT_PARK externalAgent0,
 615                        PCI_AGENT_PARK externalAgent1,
 616                        PCI_AGENT_PARK externalAgent2,
 617                        PCI_AGENT_PARK externalAgent3,
 618                        PCI_AGENT_PARK externalAgent4,
 619                        PCI_AGENT_PARK externalAgent5)
 620{
 621        unsigned int regData;
 622        unsigned int writeData;
 623
 624        GT_REG_READ (pci_arbiter_control[host], &regData);
 625        writeData = (internalAgent << 14) + (externalAgent0 << 15) +
 626                (externalAgent1 << 16) + (externalAgent2 << 17) +
 627                (externalAgent3 << 18) + (externalAgent4 << 19) +
 628                (externalAgent5 << 20);
 629        regData = (regData & ~(0x7f << 14)) | writeData;
 630        GT_REG_WRITE (pci_arbiter_control[host], regData);
 631        return true;
 632}
 633
 634/********************************************************************
 635* pciEnableBrokenAgentDetection - A master is said to be broken if it fails to
 636*                       respond to grant assertion within a window specified in
 637*                       the input value: 'brokenValue'.
 638*
 639* Inputs: unsigned char brokenValue -  A value which limits the Master to hold the
 640*                       grant without asserting frame.
 641* Returns:  Error for illegal broken value otherwise true.
 642*********************************************************************/
 643bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue)
 644{
 645        unsigned int data;
 646        unsigned int regData;
 647
 648        if (brokenValue > 0xf)
 649                return false;   /* brokenValue must be 4 bit */
 650        data = brokenValue << 3;
 651        GT_REG_READ (pci_arbiter_control[host], &regData);
 652        regData = (regData & 0xffffff87) | data;
 653        GT_REG_WRITE (pci_arbiter_control[host], regData | BIT1);
 654        return true;
 655}
 656
 657/********************************************************************
 658* pciDisableBrokenAgentDetection - This function disable the Broken agent
 659*                           Detection mechanism.
 660*                           NOTE: This operation may cause a dead lock on the
 661*                           pci0 arbitration.
 662*
 663* Inputs:   N/A
 664* Returns:  true.
 665*********************************************************************/
 666bool pciDisableBrokenAgentDetection (PCI_HOST host)
 667{
 668        unsigned int regData;
 669
 670        GT_REG_READ (pci_arbiter_control[host], &regData);
 671        regData = regData & 0xfffffffd;
 672        GT_REG_WRITE (pci_arbiter_control[host], regData);
 673        return true;
 674}
 675
 676/********************************************************************
 677* pciP2PConfig - This function set the PCI_n P2P configurate.
 678*                 For more information on the P2P read PCI spec.
 679*
 680* Inputs:  unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower
 681*                                      Boundry.
 682*          unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper
 683*                                      Boundry.
 684*          unsigned int busNum - The CPI bus number to which the PCI interface
 685*                                      is connected.
 686*          unsigned int devNum - The PCI interface's device number.
 687*
 688* Returns:  true.
 689*********************************************************************/
 690bool pciP2PConfig (PCI_HOST host, unsigned int SecondBusLow,
 691                   unsigned int SecondBusHigh,
 692                   unsigned int busNum, unsigned int devNum)
 693{
 694        unsigned int regData;
 695
 696        regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) |
 697                ((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24);
 698        GT_REG_WRITE (pci_p2p_configuration[host], regData);
 699        return true;
 700}
 701
 702/********************************************************************
 703* pciSetRegionSnoopMode - This function modifys one of the 4 regions which
 704*                          supports Cache Coherency in the PCI_n interface.
 705* Inputs: region - One of the four regions.
 706*         snoopType - There is four optional Types:
 707*                        1. No Snoop.
 708*                        2. Snoop to WT region.
 709*                        3. Snoop to WB region.
 710*                        4. Snoop & Invalidate to WB region.
 711*         baseAddress - Base Address of this region.
 712*         regionLength - Region length.
 713* Returns: false if one of the parameters is wrong otherwise return true.
 714*********************************************************************/
 715bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region,
 716                            PCI_SNOOP_TYPE snoopType,
 717                            unsigned int baseAddress,
 718                            unsigned int regionLength)
 719{
 720        unsigned int snoopXbaseAddress;
 721        unsigned int snoopXtopAddress;
 722        unsigned int data;
 723        unsigned int snoopHigh = baseAddress + regionLength;
 724
 725        if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB))
 726                return false;
 727        snoopXbaseAddress =
 728                pci_snoop_control_base_0_low[host] + 0x10 * region;
 729        snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region;
 730        if (regionLength == 0) {        /* closing the region */
 731                GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff);
 732                GT_REG_WRITE (snoopXtopAddress, 0);
 733                return true;
 734        }
 735        baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */
 736        data = (baseAddress >> 20) | snoopType << 12;
 737        GT_REG_WRITE (snoopXbaseAddress, data);
 738        snoopHigh = (snoopHigh & 0xfff00000) >> 20;
 739        GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1);
 740        return true;
 741}
 742
 743static int gt_read_config_dword (struct pci_controller *hose,
 744                                 pci_dev_t dev, int offset, u32 * value)
 745{
 746        int bus = PCI_BUS (dev);
 747
 748        if ((bus == local_buses[0]) || (bus == local_buses[1])) {
 749                *value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, offset,
 750                                           PCI_DEV (dev));
 751        } else {
 752                *value = pciOverBridgeReadConfigReg ((PCI_HOST) hose->
 753                                                     cfg_addr, offset,
 754                                                     PCI_DEV (dev), bus);
 755        }
 756
 757        return 0;
 758}
 759
 760static int gt_write_config_dword (struct pci_controller *hose,
 761                                  pci_dev_t dev, int offset, u32 value)
 762{
 763        int bus = PCI_BUS (dev);
 764
 765        if ((bus == local_buses[0]) || (bus == local_buses[1])) {
 766                pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, offset,
 767                                   PCI_DEV (dev), value);
 768        } else {
 769                pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr,
 770                                             offset, PCI_DEV (dev), bus,
 771                                             value);
 772        }
 773        return 0;
 774}
 775
 776
 777static void gt_setup_ide (struct pci_controller *hose,
 778                          pci_dev_t dev, struct pci_config_table *entry)
 779{
 780        static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 };
 781        u32 bar_response, bar_value;
 782        int bar;
 783
 784        for (bar = 0; bar < 6; bar++) {
 785                /*ronen different function for 3rd bank. */
 786                unsigned int offset =
 787                        (bar < 2) ? bar * 8 : 0x100 + (bar - 2) * 8;
 788
 789                pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + offset,
 790                                             0x0);
 791                pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + offset,
 792                                            &bar_response);
 793
 794                pciauto_region_allocate (bar_response &
 795                                         PCI_BASE_ADDRESS_SPACE_IO ? hose->
 796                                         pci_io : hose->pci_mem, ide_bar[bar],
 797                                         &bar_value);
 798
 799                pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + bar * 4,
 800                                             bar_value);
 801        }
 802}
 803
 804#ifdef CONFIG_USE_CPCIDVI
 805static void gt_setup_cpcidvi (struct pci_controller *hose,
 806                              pci_dev_t dev, struct pci_config_table *entry)
 807{
 808        u32               bar_value, pci_response;
 809
 810        pci_hose_read_config_dword (hose, dev, PCI_COMMAND, &pci_response);
 811        pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff);
 812        pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pci_response);
 813        pciauto_region_allocate (hose->pci_mem, 0x01000000, &bar_value);
 814        pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, (bar_value & 0xffffff00));
 815        pci_hose_write_config_dword (hose, dev, PCI_ROM_ADDRESS, 0x0);
 816        pciauto_region_allocate (hose->pci_mem, 0x40000, &bar_value);
 817        pci_hose_write_config_dword (hose, dev, PCI_ROM_ADDRESS, (bar_value & 0xffffff00) | 0x01);
 818        gt_cpcidvi_rom.base = bar_value & 0xffffff00;
 819        gt_cpcidvi_rom.init = 1;
 820}
 821
 822unsigned char gt_cpcidvi_in8(unsigned int offset)
 823{
 824        unsigned char     data;
 825
 826        if (gt_cpcidvi_rom.init == 0) {
 827                return(0);
 828                }
 829        data = in8((offset & 0x04) + 0x3f000 + gt_cpcidvi_rom.base);
 830        return(data);
 831}
 832
 833void gt_cpcidvi_out8(unsigned int offset, unsigned char data)
 834{
 835        unsigned int      off;
 836
 837        if (gt_cpcidvi_rom.init == 0) {
 838                return;
 839        }
 840        off = data;
 841        off = ((off << 3) & 0x7f8) + (offset & 0x4) + 0x3e000 + gt_cpcidvi_rom.base;
 842        in8(off);
 843        return;
 844}
 845#endif
 846
 847/* TODO BJW: Change this for DB64360. This was pulled from the EV64260  */
 848/* and is curently not called *. */
 849#if 0
 850static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
 851{
 852        unsigned char pin, irq;
 853
 854        pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin);
 855
 856        if (pin == 1) {         /* only allow INT A */
 857                irq = pci_irq_swizzle[(PCI_HOST) hose->
 858                                      cfg_addr][PCI_DEV (dev)];
 859                if (irq)
 860                        pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq);
 861        }
 862}
 863#endif
 864
 865struct pci_config_table gt_config_table[] = {
 866#ifdef CONFIG_USE_CPCIDVI
 867        {PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69030, PCI_CLASS_DISPLAY_VGA,
 868         PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_cpcidvi},
 869#endif
 870        {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
 871         PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide},
 872        {}
 873};
 874
 875struct pci_controller pci0_hose = {
 876/*    fixup_irq: gt_fixup_irq, */
 877        config_table:gt_config_table,
 878};
 879
 880struct pci_controller pci1_hose = {
 881/*    fixup_irq: gt_fixup_irq, */
 882        config_table:gt_config_table,
 883};
 884
 885void pci_init_board (void)
 886{
 887        unsigned int command;
 888#ifdef CONFIG_PCI_PNP
 889        unsigned int bar;
 890#endif
 891#ifdef DEBUG
 892        gt_pci_bus_mode_display (PCI_HOST0);
 893#endif
 894#ifdef CONFIG_USE_CPCIDVI
 895        gt_cpcidvi_rom.init = 0;
 896        gt_cpcidvi_rom.base = 0;
 897#endif
 898
 899        pci0_hose.config_table = gt_config_table;
 900        pci1_hose.config_table = gt_config_table;
 901
 902#ifdef CONFIG_USE_CPCIDVI
 903        gt_config_table[0].config_device =  gt_setup_cpcidvi;
 904#endif
 905        gt_config_table[1].config_device =  gt_setup_ide;
 906
 907        pci0_hose.first_busno = 0;
 908        pci0_hose.last_busno = 0xff;
 909        local_buses[0] = pci0_hose.first_busno;
 910
 911        /* PCI memory space */
 912        pci_set_region (pci0_hose.regions + 0,
 913                        CONFIG_SYS_PCI0_0_MEM_SPACE,
 914                        CONFIG_SYS_PCI0_0_MEM_SPACE,
 915                        CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM);
 916
 917        /* PCI I/O space */
 918        pci_set_region (pci0_hose.regions + 1,
 919                        CONFIG_SYS_PCI0_IO_SPACE_PCI,
 920                        CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO);
 921
 922        pci_set_ops (&pci0_hose,
 923                     pci_hose_read_config_byte_via_dword,
 924                     pci_hose_read_config_word_via_dword,
 925                     gt_read_config_dword,
 926                     pci_hose_write_config_byte_via_dword,
 927                     pci_hose_write_config_word_via_dword,
 928                     gt_write_config_dword);
 929        pci0_hose.region_count = 2;
 930
 931        pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0;
 932
 933        pci_register_hose (&pci0_hose);
 934        pciArbiterDisable(PCI_HOST0); /* on PMC modules no arbiter is used */
 935        pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
 936        command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
 937        command |= PCI_COMMAND_MASTER;
 938        pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
 939        command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
 940        command |= PCI_COMMAND_MEMORY;
 941        pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
 942
 943#ifdef CONFIG_PCI_PNP
 944        pciauto_config_init(&pci0_hose);
 945        pciauto_region_allocate(pci0_hose.pci_io, 0x400, &bar);
 946#endif
 947#ifdef CONFIG_PCI_SCAN_SHOW
 948        printf("PCI:   Bus Dev VenId DevId Class Int\n");
 949#endif
 950        pci0_hose.last_busno = pci_hose_scan_bus (&pci0_hose, pci0_hose.first_busno);
 951
 952#ifdef DEBUG
 953        gt_pci_bus_mode_display (PCI_HOST1);
 954#endif
 955        pci1_hose.first_busno = pci0_hose.last_busno + 1;
 956        pci1_hose.last_busno = 0xff;
 957        pci1_hose.current_busno = pci1_hose.first_busno;
 958        local_buses[1] = pci1_hose.first_busno;
 959
 960        /* PCI memory space */
 961        pci_set_region (pci1_hose.regions + 0,
 962                        CONFIG_SYS_PCI1_0_MEM_SPACE,
 963                        CONFIG_SYS_PCI1_0_MEM_SPACE,
 964                        CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM);
 965
 966        /* PCI I/O space */
 967        pci_set_region (pci1_hose.regions + 1,
 968                        CONFIG_SYS_PCI1_IO_SPACE_PCI,
 969                        CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO);
 970
 971        pci_set_ops (&pci1_hose,
 972                     pci_hose_read_config_byte_via_dword,
 973                     pci_hose_read_config_word_via_dword,
 974                     gt_read_config_dword,
 975                     pci_hose_write_config_byte_via_dword,
 976                     pci_hose_write_config_word_via_dword,
 977                     gt_write_config_dword);
 978
 979        pci1_hose.region_count = 2;
 980
 981        pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1;
 982
 983        pci_register_hose (&pci1_hose);
 984
 985        pciArbiterEnable (PCI_HOST1);
 986        pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1);
 987
 988        command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
 989        command |= PCI_COMMAND_MASTER;
 990        pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
 991
 992#ifdef CONFIG_PCI_PNP
 993        pciauto_config_init(&pci1_hose);
 994        pciauto_region_allocate(pci1_hose.pci_io, 0x400, &bar);
 995#endif
 996        pci1_hose.last_busno = pci_hose_scan_bus (&pci1_hose, pci1_hose.first_busno);
 997
 998        command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
 999        command |= PCI_COMMAND_MEMORY;
1000        pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);

1001
1002}
1003#endif /* of CONFIG_PCI */
1004