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12#include <asm/arch/clock.h>
13#include <asm/arch/crm_regs.h>
14#include <asm/arch/imx-regs.h>
15#include <asm/arch/iomux.h>
16#include <asm/arch/mx6-pins.h>
17#include <asm/arch/sys_proto.h>
18#include <asm/errno.h>
19#include <asm/gpio.h>
20#include <asm/imx-common/iomux-v3.h>
21#include <asm/io.h>
22#include <mmc.h>
23#include <fsl_esdhc.h>
24#include <miiphy.h>
25#include <netdev.h>
26
27DECLARE_GLOBAL_DATA_PTR;
28
29#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
30 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
31 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
32
33#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
34 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
35 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
36
37#define USDHC_PAD_CLK_CTRL (PAD_CTL_SPEED_LOW | \
38 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | \
39 PAD_CTL_HYS)
40
41#define USDHC_PAD_GPIO_CTRL (PAD_CTL_PUS_22K_UP | \
42 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \
43 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
44
45#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
46 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
47
48#define ENET_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \
49 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
50
51#define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
52 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
53
54#define ETH_PHY_RESET IMX_GPIO_NR(4, 15)
55
56int dram_init(void)
57{
58 gd->ram_size = ((phys_size_t)CONFIG_DDR_MB * 1024 * 1024);
59
60 return 0;
61}
62
63static iomux_v3_cfg_t const uart1_pads[] = {
64 MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
65 MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
66};
67
68static void setup_iomux_uart(void)
69{
70 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
71}
72
73static iomux_v3_cfg_t const usdhc2_pads[] = {
74 MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
75 MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
76 MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
77 MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
78 MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
79 MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
80 MX6_PAD_GPIO_4__SD2_CD_B | MUX_PAD_CTRL(USDHC_PAD_GPIO_CTRL),
81};
82
83#ifdef CONFIG_FSL_ESDHC
84static struct fsl_esdhc_cfg usdhc_cfg[1] = {
85 { USDHC2_BASE_ADDR },
86};
87
88int board_mmc_getcd(struct mmc *mmc)
89{
90 return 1;
91}
92
93int board_mmc_init(bd_t *bis)
94{
95 imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
96 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
97
98 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
99}
100#endif
101
102#ifdef CONFIG_FEC_MXC
103static iomux_v3_cfg_t const enet_pads[] = {
104 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
105 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
106
107 MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
108
109 MX6_PAD_DI0_PIN2__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
110
111 MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL),
112 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(NO_PAD_CTRL),
113 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
114 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
115 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
116 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
117 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
118
119 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK),
120 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
121 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
122 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
123 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
124 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
125 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
126};
127
128static void setup_iomux_enet(void)
129{
130 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
131
132 gpio_direction_output(ETH_PHY_RESET, 0);
133 mdelay(2);
134 gpio_set_value(ETH_PHY_RESET, 1);
135}
136
137int board_phy_config(struct phy_device *phydev)
138{
139 if (phydev->drv->config)
140 phydev->drv->config(phydev);
141
142 return 0;
143}
144
145int board_eth_init(bd_t *bis)
146{
147 struct iomuxc_base_regs *const iomuxc_regs =
148 (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
149
150 int ret = enable_fec_anatop_clock(ENET_25MHz);
151 if (ret)
152 return ret;
153
154
155 setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
156
157 setup_iomux_enet();
158
159 return cpu_eth_init(bis);
160}
161#endif
162
163int board_early_init_f(void)
164{
165 setup_iomux_uart();
166
167 return 0;
168}
169
170int board_init(void)
171{
172
173 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
174
175 return 0;
176}
177
178int checkboard(void)
179{
180 puts("Board: Hummingboard\n");
181
182 return 0;
183}
184
