1
2
3
4
5
6
7
8
9
10
11#ifndef PATA_BFIN_H
12#define PATA_BFIN_H
13
14#include <asm/blackfin_local.h>
15
16struct ata_ioports {
17 unsigned long cmd_addr;
18 unsigned long data_addr;
19 unsigned long error_addr;
20 unsigned long feature_addr;
21 unsigned long nsect_addr;
22 unsigned long lbal_addr;
23 unsigned long lbam_addr;
24 unsigned long lbah_addr;
25 unsigned long device_addr;
26 unsigned long status_addr;
27 unsigned long command_addr;
28 unsigned long altstatus_addr;
29 unsigned long ctl_addr;
30 unsigned long bmdma_addr;
31 unsigned long scr_addr;
32};
33
34struct ata_port {
35 unsigned int port_no;
36 struct ata_ioports ioaddr;
37 unsigned long flag;
38 unsigned int ata_mode;
39 unsigned char ctl_reg;
40 unsigned char last_ctl;
41 unsigned char dev_mask;
42};
43
44#define DRV_NAME "pata-bfin"
45#define DRV_VERSION "0.9"
46#define __iomem
47
48#define ATA_REG_CTRL 0x0E
49#define ATA_REG_ALTSTATUS ATA_REG_CTRL
50#define ATA_TMOUT_BOOT 30000
51#define ATA_TMOUT_BOOT_QUICK 7000
52
53#define PATA_BFIN_WAIT_TIMEOUT 10000
54#define PATA_DEV_NUM_PER_PORT 2
55
56
57#define ATAPI_OFFSET_CONTROL 0x00
58#define ATAPI_OFFSET_STATUS 0x04
59#define ATAPI_OFFSET_DEV_ADDR 0x08
60#define ATAPI_OFFSET_DEV_TXBUF 0x0c
61#define ATAPI_OFFSET_DEV_RXBUF 0x10
62#define ATAPI_OFFSET_INT_MASK 0x14
63#define ATAPI_OFFSET_INT_STATUS 0x18
64#define ATAPI_OFFSET_XFER_LEN 0x1c
65#define ATAPI_OFFSET_LINE_STATUS 0x20
66#define ATAPI_OFFSET_SM_STATE 0x24
67#define ATAPI_OFFSET_TERMINATE 0x28
68#define ATAPI_OFFSET_PIO_TFRCNT 0x2c
69#define ATAPI_OFFSET_DMA_TFRCNT 0x30
70#define ATAPI_OFFSET_UMAIN_TFRCNT 0x34
71#define ATAPI_OFFSET_UDMAOUT_TFRCNT 0x38
72#define ATAPI_OFFSET_REG_TIM_0 0x40
73#define ATAPI_OFFSET_PIO_TIM_0 0x44
74#define ATAPI_OFFSET_PIO_TIM_1 0x48
75#define ATAPI_OFFSET_MULTI_TIM_0 0x50
76#define ATAPI_OFFSET_MULTI_TIM_1 0x54
77#define ATAPI_OFFSET_MULTI_TIM_2 0x58
78#define ATAPI_OFFSET_ULTRA_TIM_0 0x60
79#define ATAPI_OFFSET_ULTRA_TIM_1 0x64
80#define ATAPI_OFFSET_ULTRA_TIM_2 0x68
81#define ATAPI_OFFSET_ULTRA_TIM_3 0x6c
82
83
84#define ATAPI_GET_CONTROL(base)\
85 bfin_read16(base + ATAPI_OFFSET_CONTROL)
86#define ATAPI_SET_CONTROL(base, val)\
87 bfin_write16(base + ATAPI_OFFSET_CONTROL, val)
88#define ATAPI_GET_STATUS(base)\
89 bfin_read16(base + ATAPI_OFFSET_STATUS)
90#define ATAPI_GET_DEV_ADDR(base)\
91 bfin_read16(base + ATAPI_OFFSET_DEV_ADDR)
92#define ATAPI_SET_DEV_ADDR(base, val)\
93 bfin_write16(base + ATAPI_OFFSET_DEV_ADDR, val)
94#define ATAPI_GET_DEV_TXBUF(base)\
95 bfin_read16(base + ATAPI_OFFSET_DEV_TXBUF)
96#define ATAPI_SET_DEV_TXBUF(base, val)\
97 bfin_write16(base + ATAPI_OFFSET_DEV_TXBUF, val)
98#define ATAPI_GET_DEV_RXBUF(base)\
99 bfin_read16(base + ATAPI_OFFSET_DEV_RXBUF)
100#define ATAPI_SET_DEV_RXBUF(base, val)\
101 bfin_write16(base + ATAPI_OFFSET_DEV_RXBUF, val)
102#define ATAPI_GET_INT_MASK(base)\
103 bfin_read16(base + ATAPI_OFFSET_INT_MASK)
104#define ATAPI_SET_INT_MASK(base, val)\
105 bfin_write16(base + ATAPI_OFFSET_INT_MASK, val)
106#define ATAPI_GET_INT_STATUS(base)\
107 bfin_read16(base + ATAPI_OFFSET_INT_STATUS)
108#define ATAPI_SET_INT_STATUS(base, val)\
109 bfin_write16(base + ATAPI_OFFSET_INT_STATUS, val)
110#define ATAPI_GET_XFER_LEN(base)\
111 bfin_read16(base + ATAPI_OFFSET_XFER_LEN)
112#define ATAPI_SET_XFER_LEN(base, val)\
113 bfin_write16(base + ATAPI_OFFSET_XFER_LEN, val)
114#define ATAPI_GET_LINE_STATUS(base)\
115 bfin_read16(base + ATAPI_OFFSET_LINE_STATUS)
116#define ATAPI_GET_SM_STATE(base)\
117 bfin_read16(base + ATAPI_OFFSET_SM_STATE)
118#define ATAPI_GET_TERMINATE(base)\
119 bfin_read16(base + ATAPI_OFFSET_TERMINATE)
120#define ATAPI_SET_TERMINATE(base, val)\
121 bfin_write16(base + ATAPI_OFFSET_TERMINATE, val)
122#define ATAPI_GET_PIO_TFRCNT(base)\
123 bfin_read16(base + ATAPI_OFFSET_PIO_TFRCNT)
124#define ATAPI_GET_DMA_TFRCNT(base)\
125 bfin_read16(base + ATAPI_OFFSET_DMA_TFRCNT)
126#define ATAPI_GET_UMAIN_TFRCNT(base)\
127 bfin_read16(base + ATAPI_OFFSET_UMAIN_TFRCNT)
128#define ATAPI_GET_UDMAOUT_TFRCNT(base)\
129 bfin_read16(base + ATAPI_OFFSET_UDMAOUT_TFRCNT)
130#define ATAPI_GET_REG_TIM_0(base)\
131 bfin_read16(base + ATAPI_OFFSET_REG_TIM_0)
132#define ATAPI_SET_REG_TIM_0(base, val)\
133 bfin_write16(base + ATAPI_OFFSET_REG_TIM_0, val)
134#define ATAPI_GET_PIO_TIM_0(base)\
135 bfin_read16(base + ATAPI_OFFSET_PIO_TIM_0)
136#define ATAPI_SET_PIO_TIM_0(base, val)\
137 bfin_write16(base + ATAPI_OFFSET_PIO_TIM_0, val)
138#define ATAPI_GET_PIO_TIM_1(base)\
139 bfin_read16(base + ATAPI_OFFSET_PIO_TIM_1)
140#define ATAPI_SET_PIO_TIM_1(base, val)\
141 bfin_write16(base + ATAPI_OFFSET_PIO_TIM_1, val)
142#define ATAPI_GET_MULTI_TIM_0(base)\
143 bfin_read16(base + ATAPI_OFFSET_MULTI_TIM_0)
144#define ATAPI_SET_MULTI_TIM_0(base, val)\
145 bfin_write16(base + ATAPI_OFFSET_MULTI_TIM_0, val)
146#define ATAPI_GET_MULTI_TIM_1(base)\
147 bfin_read16(base + ATAPI_OFFSET_MULTI_TIM_1)
148#define ATAPI_SET_MULTI_TIM_1(base, val)\
149 bfin_write16(base + ATAPI_OFFSET_MULTI_TIM_1, val)
150#define ATAPI_GET_MULTI_TIM_2(base)\
151 bfin_read16(base + ATAPI_OFFSET_MULTI_TIM_2)
152#define ATAPI_SET_MULTI_TIM_2(base, val)\
153 bfin_write16(base + ATAPI_OFFSET_MULTI_TIM_2, val)
154#define ATAPI_GET_ULTRA_TIM_0(base)\
155 bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_0)
156#define ATAPI_SET_ULTRA_TIM_0(base, val)\
157 bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_0, val)
158#define ATAPI_GET_ULTRA_TIM_1(base)\
159 bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_1)
160#define ATAPI_SET_ULTRA_TIM_1(base, val)\
161 bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_1, val)
162#define ATAPI_GET_ULTRA_TIM_2(base)\
163 bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_2)
164#define ATAPI_SET_ULTRA_TIM_2(base, val)\
165 bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_2, val)
166#define ATAPI_GET_ULTRA_TIM_3(base)\
167 bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_3)
168#define ATAPI_SET_ULTRA_TIM_3(base, val)\
169 bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_3, val)
170
171#endif
172
