1/* 2 * Copyright (C) 2004 Arabella Software Ltd. 3 * Yuli Barcohen <yuli@arabellasw.com> 4 * 5 * Support for Interphase iSPAN Communications Controllers 6 * (453x and others). Tested on 4532. 7 * 8 * Derived from iSPAN 4539 port (iphase4539) by 9 * Wolfgang Grandegger <wg@denx.de> 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13#ifndef __CONFIG_H 14#define __CONFIG_H 15 16#define CONFIG_ISPAN /* ...on one of Interphase iSPAN boards */ 17#define CONFIG_CPM2 1 /* Has a CPM2 */ 18 19#define CONFIG_SYS_TEXT_BASE 0xFE7A0000 20 21/*----------------------------------------------------------------------- 22 * Select serial console configuration 23 * 24 * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then 25 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 26 * for SCC). 27 * 28 * If CONFIG_CONS_NONE is defined, then the serial console routines must be 29 * defined elsewhere (for example, on the cogent platform, there are serial 30 * ports on the motherboard which are used for the serial console - see 31 * cogent/cma101/serial.[ch]). 32 */ 33#define CONFIG_CONS_ON_SMC /* Define if console on SMC */ 34#undef CONFIG_CONS_ON_SCC /* Define if console on SCC */ 35#undef CONFIG_CONS_NONE /* Define if console on something else */ 36#define CONFIG_CONS_INDEX 1 /* Which serial channel for console */ 37 38/*----------------------------------------------------------------------- 39 * Select Ethernet configuration 40 * 41 * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then 42 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 43 * for FCC). 44 * 45 * If CONFIG_ETHER_NONE is defined, then either the Ethernet routines must 46 * be defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. 47 */ 48#undef CONFIG_ETHER_ON_SCC /* Define if Ethernet on SCC */ 49#define CONFIG_ETHER_ON_FCC /* Define if Ethernet on FCC */ 50#undef CONFIG_ETHER_NONE /* Define if Ethernet on something else */ 51#define CONFIG_ETHER_INDEX 3 /* Which channel for Ethernrt */ 52 53#ifdef CONFIG_ETHER_ON_FCC 54 55#if CONFIG_ETHER_INDEX == 3 56 57#define CONFIG_SYS_PHY_ADDR 0 58#define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK14 | CMXFCR_TF3CS_CLK16) 59#define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK) 60 61#endif /* CONFIG_ETHER_INDEX == 3 */ 62 63#define CONFIG_SYS_CPMFCR_RAMTYPE 0 64#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) 65 66#define CONFIG_MII /* MII PHY management */ 67#define CONFIG_BITBANGMII /* Bit-bang MII PHY management */ 68/* 69 * GPIO pins used for bit-banged MII communications 70 */ 71#define MDIO_PORT 3 /* Port D */ 72#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ 73 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) 74#define MDC_DECLARE MDIO_DECLARE 75 76 77#define CONFIG_SYS_MDIO_PIN 0x00040000 /* PD13 */ 78#define CONFIG_SYS_MDC_PIN 0x00080000 /* PD12 */ 79 80#define MDIO_ACTIVE (iop->pdir |= CONFIG_SYS_MDIO_PIN) 81#define MDIO_TRISTATE (iop->pdir &= ~CONFIG_SYS_MDIO_PIN) 82#define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0) 83 84#define MDIO(bit) if(bit) iop->pdat |= CONFIG_SYS_MDIO_PIN; \ 85 else iop->pdat &= ~CONFIG_SYS_MDIO_PIN 86 87#define MDC(bit) if(bit) iop->pdat |= CONFIG_SYS_MDC_PIN; \ 88 else iop->pdat &= ~CONFIG_SYS_MDC_PIN 89 90#define MIIDELAY udelay(1) 91 92#endif /* CONFIG_ETHER_ON_FCC */ 93 94#define CONFIG_8260_CLKIN 65536000 /* in Hz */ 95#define CONFIG_BAUDRATE 38400 96 97 98/* 99 * BOOTP options 100 */ 101#define CONFIG_BOOTP_BOOTFILESIZE 102#define CONFIG_BOOTP_BOOTPATH 103#define CONFIG_BOOTP_GATEWAY 104#define CONFIG_BOOTP_HOSTNAME 105 106 107/* 108 * Command line configuration. 109 */ 110#include <config_cmd_default.h> 111 112#define CONFIG_CMD_ASKENV 113#define CONFIG_CMD_DHCP 114#define CONFIG_CMD_IMMAP 115#define CONFIG_CMD_MII 116#define CONFIG_CMD_PING 117#define CONFIG_CMD_REGINFO 118 119 120#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 121#define CONFIG_BOOTCOMMAND "bootm fe010000" /* autoboot command */ 122#define CONFIG_BOOTARGS "root=/dev/ram rw" 123 124#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */ 125#undef CONFIG_WATCHDOG /* Disable platform specific watchdog */ 126 127/*----------------------------------------------------------------------- 128 * Miscellaneous configurable options 129 */ 130#define CONFIG_SYS_HUSH_PARSER 131#define CONFIG_SYS_LONGHELP /* #undef to save memory */ 132#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 133#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ 134#define CONFIG_SYS_MAXARGS 16 /* Max number of command args */ 135#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 136 137#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ 138#define CONFIG_SYS_MEMTEST_END 0x03B00000 /* 1 ... 59 MB in SDRAM */ 139 140#define CONFIG_SYS_LOAD_ADDR 0x100000 /* Default load address */ 141 142#define CONFIG_SYS_RESET_ADDRESS 0x09900000 143 144#define CONFIG_MISC_INIT_R /* We need misc_init_r() */ 145 146/*----------------------------------------------------------------------- 147 * For booting Linux, the board info and command line data 148 * have to be in the first 8 MB of memory, since this is 149 * the maximum mapped by the Linux kernel during initialization. 150 */ 151#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 152 153#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 154#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ 155#ifdef CONFIG_BZIP2 156#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */ 157#else 158#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */ 159#endif /* CONFIG_BZIP2 */ 160 161/*----------------------------------------------------------------------- 162 * FLASH organization 163 */ 164#define CONFIG_SYS_FLASH_BASE 0xFE000000 165#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ 166#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ 167#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max num of memory banks */ 168#define CONFIG_SYS_MAX_FLASH_SECT 142 /* Max num of sects on one chip */ 169 170/* Environment is in flash, there is little space left in Serial EEPROM */ 171#define CONFIG_ENV_IS_IN_FLASH 172#define CONFIG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */ 173#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 174#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 175#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 176#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 177 178/*----------------------------------------------------------------------- 179 * Hard Reset Configuration Words 180 * 181 * If you change bits in the HRCW, you must also change the CONFIG_SYS_* 182 * defines for the various registers affected by the HRCW e.g. changing 183 * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. 184 */ 185/* 0x1686B245 */ 186#define CONFIG_SYS_HRCW_MASTER (HRCW_EBM | HRCW_BPS01 | HRCW_CIP |\ 187 HRCW_L2CPC10 | HRCW_ISB110 |\ 188 HRCW_BMS | HRCW_MMR11 | HRCW_APPC10 |\ 189 HRCW_CS10PC01 | HRCW_MODCK_H0101 \ 190 ) 191/* No slaves */ 192#define CONFIG_SYS_HRCW_SLAVE1 0 193#define CONFIG_SYS_HRCW_SLAVE2 0 194#define CONFIG_SYS_HRCW_SLAVE3 0 195#define CONFIG_SYS_HRCW_SLAVE4 0 196#define CONFIG_SYS_HRCW_SLAVE5 0 197#define CONFIG_SYS_HRCW_SLAVE6 0 198#define CONFIG_SYS_HRCW_SLAVE7 0 199 200/*----------------------------------------------------------------------- 201 * Internal Memory Mapped Register 202 */ 203#define CONFIG_SYS_IMMR 0xF0F00000 204#ifdef CONFIG_SYS_REV_B 205#define CONFIG_SYS_DEFAULT_IMMR 0xFF000000 206#endif /* CONFIG_SYS_REV_B */ 207/*----------------------------------------------------------------------- 208 * Definitions for initial stack pointer and data area (in DPRAM) 209 */ 210#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 211#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ 212#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 213#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 214 215/*----------------------------------------------------------------------- 216 * Cache Configuration 217 */ 218#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ 219 220/*----------------------------------------------------------------------- 221 * HIDx - Hardware Implementation-dependent Registers 2-11 222 *----------------------------------------------------------------------- 223 * HID0 also contains cache control. 224 * 225 * HID1 has only read-only information - nothing to set. 226 */ 227#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ 228 HID0_IFEM|HID0_ABE) 229#define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE) 230#define CONFIG_SYS_HID2 0 231 232/*----------------------------------------------------------------------- 233 * RMR - Reset Mode Register 5-5 234 *----------------------------------------------------------------------- 235 * turn on Checkstop Reset Enable 236 */ 237#define CONFIG_SYS_RMR RMR_CSRE 238 239/*----------------------------------------------------------------------- 240 * BCR - Bus Configuration 4-25 241 *----------------------------------------------------------------------- 242 */ 243#define CONFIG_SYS_BCR 0xA01C0000 244 245/*----------------------------------------------------------------------- 246 * SIUMCR - SIU Module Configuration 4-31 247 *----------------------------------------------------------------------- 248 */ 249#define CONFIG_SYS_SIUMCR 0x42250000/* 0x4205C000 */ 250 251/*----------------------------------------------------------------------- 252 * SYPCR - System Protection Control 4-35 253 * SYPCR can only be written once after reset! 254 *----------------------------------------------------------------------- 255 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable 256 */ 257#if defined (CONFIG_WATCHDOG) 258#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ 259 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) 260#else 261#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ 262 SYPCR_SWRI|SYPCR_SWP) 263#endif /* CONFIG_WATCHDOG */ 264 265/*----------------------------------------------------------------------- 266 * TMCNTSC - Time Counter Status and Control 4-40 267 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, 268 * and enable Time Counter 269 *----------------------------------------------------------------------- 270 */ 271#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) 272 273/*----------------------------------------------------------------------- 274 * PISCR - Periodic Interrupt Status and Control 4-42 275 *----------------------------------------------------------------------- 276 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable 277 * Periodic timer 278 */ 279#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) 280 281/*----------------------------------------------------------------------- 282 * SCCR - System Clock Control 9-8 283 *----------------------------------------------------------------------- 284 * Ensure DFBRG is Divide by 16 285 */ 286#define CONFIG_SYS_SCCR SCCR_DFBRG01 287 288/*----------------------------------------------------------------------- 289 * RCCR - RISC Controller Configuration 13-7 290 *----------------------------------------------------------------------- 291 */ 292#define CONFIG_SYS_RCCR 0 293 294/*----------------------------------------------------------------------- 295 * Init Memory Controller: 296 * 297 * Bank Bus Machine PortSize Device 298 * ---- --- ------- ----------------------------- ------ 299 * 0 60x GPCM 8 bit (Rev.B)/16 bit (Rev.D) Flash 300 * 1 60x SDRAM 64 bit SDRAM 301 * 2 Local SDRAM 32 bit SDRAM 302 */ 303#define CONFIG_SYS_USE_FIRMWARE /* If defined - do not initialise memory 304 controller, rely on initialisation 305 performed by the Interphase boot firmware. 306 */ 307 308#define CONFIG_SYS_OR0_PRELIM 0xFE000882 309#ifdef CONFIG_SYS_REV_B 310#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BRx_PS_8 | BRx_V) 311#else /* Rev. D */ 312#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BRx_PS_16 | BRx_V) 313#endif /* CONFIG_SYS_REV_B */ 314 315#define CONFIG_SYS_MPTPR 0x7F00 316 317/* Please note that 60x SDRAM MUST start at 0 */ 318#define CONFIG_SYS_SDRAM_BASE 0x00000000 319#define CONFIG_SYS_60x_BR 0x00000041 320#define CONFIG_SYS_60x_OR 0xF0002CD0 321#define CONFIG_SYS_PSDMR 0x0049929A 322#define CONFIG_SYS_PSRT 0x07 323 324#define CONFIG_SYS_LSDRAM_BASE 0xF7000000 325#define CONFIG_SYS_LOC_BR 0x00001861 326#define CONFIG_SYS_LOC_OR 0xFF803280 327#define CONFIG_SYS_LSDMR 0x8285A552 328#define CONFIG_SYS_LSRT 0x07 329 330#endif /* __CONFIG_H */ 331