1/* 2 * (C) Copyright 2000, 2001 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * (C) Copyright 2001 6 * James F. Dougherty (jfd@cs.stanford.edu) 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11/* 12 * 13 * Configuration settings for the MOUSSE board. 14 * See also: http://www.vooha.com/ 15 * 16 */ 17 18/* ------------------------------------------------------------------------- */ 19 20/* 21 * board/config.h - configuration options, board specific 22 */ 23 24#ifndef __CONFIG_H 25#define __CONFIG_H 26 27/* 28 * High Level Configuration Options 29 * (easy to change) 30 */ 31 32#define CONFIG_MPC8240 1 33#define CONFIG_MOUSSE 1 34 35#define CONFIG_SYS_TEXT_BASE 0xFFF00000 36#define CONFIG_SYS_LDSCRIPT "board/mousse/u-boot.lds" 37 38#define CONFIG_SYS_ADDR_MAP_B 1 39 40#define CONFIG_CONS_INDEX 1 41#define CONFIG_BAUDRATE 9600 42#if 1 43#define CONFIG_BOOTCOMMAND "tftp 100000 vmlinux.img;bootm" /* autoboot command */ 44#else 45#define CONFIG_BOOTCOMMAND "bootm ffe10000" 46#endif 47#define CONFIG_BOOTARGS "console=ttyS0 root=/dev/nfs rw nfsroot=209.128.93.133:/boot nfsaddrs=209.128.93.133:209.128.93.138" 48#define CONFIG_BOOTDELAY 3 49 50 51/* 52 * BOOTP options 53 */ 54#define CONFIG_BOOTP_BOOTFILESIZE 55#define CONFIG_BOOTP_BOOTPATH 56#define CONFIG_BOOTP_GATEWAY 57#define CONFIG_BOOTP_HOSTNAME 58 59 60/* 61 * Command line configuration. 62 */ 63#include <config_cmd_default.h> 64 65#define CONFIG_CMD_ASKENV 66#define CONFIG_CMD_DATE 67 68 69#define CONFIG_ENV_OVERWRITE 1 70#define CONFIG_ETH_ADDR "00:10:18:10:00:06" 71 72#define CONFIG_DOS_PARTITION 1 /* MSDOS bootable partitiion support */ 73 74#include "../board/mousse/mousse.h" 75 76/* 77 * Miscellaneous configurable options 78 */ 79#undef CONFIG_SYS_LONGHELP /* undef to save memory */ 80#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 81#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 82#define CONFIG_SYS_MAXARGS 8 /* Max number of command args */ 83 84#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 85#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */ 86 87/*----------------------------------------------------------------------- 88 * Start addresses for the final memory configuration 89 * (Set up by the startup code) 90 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 91 */ 92#define CONFIG_SYS_SDRAM_BASE 0x00000000 93 94#ifdef DEBUG 95#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_SDRAM_BASE 96#else 97#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 98#endif 99 100#ifdef DEBUG 101#define CONFIG_SYS_MONITOR_LEN (4 << 20) /* lots of mem ... */ 102#else 103#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* 512K PLCC bootrom */ 104#endif 105#define CONFIG_SYS_MALLOC_LEN (2*(4096 << 10)) /* 2*4096kB for malloc() */ 106 107#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */ 108#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ 109 110 111#define CONFIG_SYS_EUMB_ADDR 0xFC000000 112 113#define CONFIG_SYS_ISA_MEM 0xFD000000 114#define CONFIG_SYS_ISA_IO 0xFE000000 115 116#define CONFIG_SYS_FLASH_BASE 0xFFF00000 117#define CONFIG_SYS_FLASH_SIZE ((uint)(512 * 1024)) 118#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 119#define FLASH_BASE0_PRELIM 0xFFF00000 /* 512K PLCC FLASH/AM29F040*/ 120#define FLASH_BASE0_SIZE 0x80000 /* 512K */ 121#define FLASH_BASE1_PRELIM 0xFFE10000 /* AMD 29LV160DB 122 1MB - 64K FLASH0 SEG =960K 123 (size=0xf0000)*/ 124 125/* 126 * NS16550 Configuration 127 */ 128#define CONFIG_SYS_NS16550 129#define CONFIG_SYS_NS16550_SERIAL 130 131#define CONFIG_SYS_NS16550_REG_SIZE 1 132 133#define CONFIG_SYS_NS16550_CLK 18432000 134 135#define CONFIG_SYS_NS16550_COM1 0xFFE08080 136 137/*----------------------------------------------------------------------- 138 * Definitions for initial stack pointer and data area (in DPRAM) 139 */ 140#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MONITOR_LEN 141#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ 142#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 143#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 144 145/* 146 * Low Level Configuration Settings 147 * (address mappings, register initial values, etc.) 148 * You should know what you are doing if you make changes here. 149 * For the detail description refer to the MPC8240 user's manual. 150 */ 151 152#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ 153#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 2 154 155#define CONFIG_SYS_ETH_DEV_FN 0x00 156#define CONFIG_SYS_ETH_IOBASE 0x00104000 157 158 159 /* Bit-field values for MCCR1. 160 */ 161#define CONFIG_SYS_ROMNAL 8 162#define CONFIG_SYS_ROMFAL 8 163 164 /* Bit-field values for MCCR2. 165 */ 166#define CONFIG_SYS_REFINT 0xf5 /* Refresh interval */ 167 168 /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. 169 */ 170#define CONFIG_SYS_BSTOPRE 0x79 171 172#ifdef INCLUDE_ECC 173#define USE_ECC 1 174#else /* INCLUDE_ECC */ 175#define USE_ECC 0 176#endif /* INCLUDE_ECC */ 177 178 179 /* Bit-field values for MCCR3. 180 */ 181#define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */ 182#define CONFIG_SYS_RDLAT (4+USE_ECC) /* Data latancy from read command */ 183 184 /* Bit-field values for MCCR4. 185 */ 186#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */ 187#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */ 188#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */ 189#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */ 190#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length */ 191#define CONFIG_SYS_ACTORW 2 192#define CONFIG_SYS_REGISTERD_TYPE_BUFFER (1-USE_ECC) 193 194/* Memory bank settings. 195 * Only bits 20-29 are actually used from these vales to set the 196 * start/end addresses. The upper two bits will always be 0, and the lower 197 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end 198 * address. Refer to the MPC8240 book. 199 */ 200#define CONFIG_SYS_RAM_SIZE 0x04000000 /* 64MB */ 201 202 203#define CONFIG_SYS_BANK0_START 0x00000000 204#define CONFIG_SYS_BANK0_END (CONFIG_SYS_RAM_SIZE - 1) 205#define CONFIG_SYS_BANK0_ENABLE 1 206#define CONFIG_SYS_BANK1_START 0x3ff00000 207#define CONFIG_SYS_BANK1_END 0x3fffffff 208#define CONFIG_SYS_BANK1_ENABLE 0 209#define CONFIG_SYS_BANK2_START 0x3ff00000 210#define CONFIG_SYS_BANK2_END 0x3fffffff 211#define CONFIG_SYS_BANK2_ENABLE 0 212#define CONFIG_SYS_BANK3_START 0x3ff00000 213#define CONFIG_SYS_BANK3_END 0x3fffffff 214#define CONFIG_SYS_BANK3_ENABLE 0 215#define CONFIG_SYS_BANK4_START 0x3ff00000 216#define CONFIG_SYS_BANK4_END 0x3fffffff 217#define CONFIG_SYS_BANK4_ENABLE 0 218#define CONFIG_SYS_BANK5_START 0x3ff00000 219#define CONFIG_SYS_BANK5_END 0x3fffffff 220#define CONFIG_SYS_BANK5_ENABLE 0 221#define CONFIG_SYS_BANK6_START 0x3ff00000 222#define CONFIG_SYS_BANK6_END 0x3fffffff 223#define CONFIG_SYS_BANK6_ENABLE 0 224#define CONFIG_SYS_BANK7_START 0x3ff00000 225#define CONFIG_SYS_BANK7_END 0x3fffffff 226#define CONFIG_SYS_BANK7_ENABLE 0 227 228#define CONFIG_SYS_ODCR 0x7f 229 230 231#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 reatins the currently accessed page in memory 232 see 8240 book for details*/ 233#define PCI_MEM_SPACE1_START 0x80000000 234#define PCI_MEM_SPACE2_START 0xfd000000 235 236/* IBAT/DBAT Configuration */ 237/* Ram: 64MB, starts at address-0, r/w instruction/data */ 238#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP) 239#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 240#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 241#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 242 243/* MPLD/Port-X I/O Space : data and instruction read/write, cache-inhibit */ 244#define CONFIG_SYS_IBAT1U (PORTX_DEV_BASE | BATU_BL_128M | BATU_VS | BATU_VP) 245#if 0 246#define CONFIG_SYS_IBAT1L (PORTX_DEV_BASE | BATL_PP_10 | BATL_MEMCOHERENCE |\ 247 BATL_WRITETHROUGH | BATL_CACHEINHIBIT) 248#else 249#define CONFIG_SYS_IBAT1L (PORTX_DEV_BASE | BATL_PP_10 |BATL_CACHEINHIBIT) 250#endif 251#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 252#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 253 254/* PCI Memory region 1: 0x8XXX_XXXX PCI Mem space: EUMBAR, etc - 16MB */ 255#define CONFIG_SYS_IBAT2U (PCI_MEM_SPACE1_START|BATU_BL_16M | BATU_VS | BATU_VP) 256#define CONFIG_SYS_IBAT2L (PCI_MEM_SPACE1_START|BATL_PP_10 | BATL_GUARDEDSTORAGE|BATL_CACHEINHIBIT) 257#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 258#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 259 260/* PCI Memory region 2: PCI Devices in 0xFD space */ 261#define CONFIG_SYS_IBAT3U (PCI_MEM_SPACE2_START|BATU_BL_16M | BATU_VS | BATU_VP) 262#define CONFIG_SYS_IBAT3L (PCI_MEM_SPACE2_START|BATL_PP_10 | BATL_GUARDEDSTORAGE | BATL_CACHEINHIBIT) 263#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 264#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 265 266 267/* 268 * For booting Linux, the board info and command line data 269 * have to be in the first 8 MB of memory, since this is 270 * the maximum mapped by the Linux kernel during initialization. 271 */ 272#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 273 274/*----------------------------------------------------------------------- 275 * FLASH organization 276 */ 277#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* Max number of flash banks */ 278#define CONFIG_SYS_MAX_FLASH_SECT 64 /* Max number of sectors in one bank */ 279 280#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 281#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 282 283#if 0 284#define CONFIG_ENV_IS_IN_FLASH 1 285#define CONFIG_ENV_OFFSET 0x8000 /* Offset of the Environment Sector */ 286#define CONFIG_ENV_SIZE 0x4000 /* Size of the Environment Sector */ 287#else 288#define CONFIG_ENV_IS_IN_NVRAM 1 289#define CONFIG_ENV_ADDR NV_OFF_U_BOOT_ADDR /* PortX NVM Free addr*/ 290#define CONFIG_ENV_OFFSET CONFIG_ENV_ADDR 291#define CONFIG_ENV_SIZE NV_U_BOOT_ENV_SIZE /* 2K */ 292#endif 293/*----------------------------------------------------------------------- 294 * Cache Configuration 295 */ 296#define CONFIG_SYS_CACHELINE_SIZE 16 297 298/* Localizations */ 299#if 0 300#define CONFIG_ETHADDR 0:0:0:0:1:d 301#define CONFIG_IPADDR 172.16.40.113 302#define CONFIG_SERVERIP 172.16.40.111 303#else 304#define CONFIG_ETHADDR 0:0:0:0:1:d 305#define CONFIG_IPADDR 209.128.93.138 306#define CONFIG_SERVERIP 209.128.93.133 307#endif 308 309/*----------------------------------------------------------------------- 310 * PCI stuff 311 *----------------------------------------------------------------------- 312 */ 313#define CONFIG_PCI /* include pci support */ 314#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 315#undef CONFIG_PCI_PNP 316 317 318#define CONFIG_TULIP 319 320#endif /* __CONFIG_H */ 321