1/* 2 * (C) Copyright 2001-2005 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8/* 9 * board/config.h - configuration options, board specific 10 */ 11 12#ifndef __CONFIG_H 13#define __CONFIG_H 14 15#undef CONFIG_SYS_RAMBOOT 16 17/* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 22#define CONFIG_PM826 1 /* ...on a PM8260 module */ 23#define CONFIG_CPM2 1 /* Has a CPM2 */ 24 25#ifndef CONFIG_SYS_TEXT_BASE 26#define CONFIG_SYS_TEXT_BASE 0xFF000000 /* Standard: boot 64-bit flash */ 27#endif 28 29#undef CONFIG_DB_CR826_J30x_ON /* J30x jumpers on D.B. carrier */ 30 31#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 32 33#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" 34 35#undef CONFIG_BOOTARGS 36#define CONFIG_BOOTCOMMAND \ 37 "bootp; " \ 38 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ 39 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ 40 "bootm" 41 42/* enable I2C and select the hardware/software driver */ 43#define CONFIG_SYS_I2C 44#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ 45#define CONFIG_SYS_I2C_SOFT_SPEED 50000 46#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE 47/* 48 * Software (bit-bang) I2C driver configuration 49 */ 50#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ 51#define I2C_ACTIVE (iop->pdir |= 0x00010000) 52#define I2C_TRISTATE (iop->pdir &= ~0x00010000) 53#define I2C_READ ((iop->pdat & 0x00010000) != 0) 54#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ 55 else iop->pdat &= ~0x00010000 56#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ 57 else iop->pdat &= ~0x00020000 58#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ 59 60 61#define CONFIG_RTC_PCF8563 62#define CONFIG_SYS_I2C_RTC_ADDR 0x51 63 64/* 65 * select serial console configuration 66 * 67 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then 68 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 69 * for SCC). 70 * 71 * if CONFIG_CONS_NONE is defined, then the serial console routines must 72 * defined elsewhere (for example, on the cogent platform, there are serial 73 * ports on the motherboard which are used for the serial console - see 74 * cogent/cma101/serial.[ch]). 75 */ 76#define CONFIG_CONS_ON_SMC /* define if console on SMC */ 77#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ 78#undef CONFIG_CONS_NONE /* define if console on something else*/ 79#define CONFIG_CONS_INDEX 2 /* which serial channel for console */ 80 81/* 82 * select ethernet configuration 83 * 84 * if CONFIG_ETHER_ON_SCC is selected, then 85 * - CONFIG_ETHER_INDEX must be set to the channel number (1-4) 86 * 87 * if CONFIG_ETHER_ON_FCC is selected, then 88 * - one or more CONFIG_ETHER_ON_FCCx (x=1,2,3) must also be selected 89 * 90 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be 91 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. 92 */ 93#undef CONFIG_ETHER_NONE /* define if ether on something else */ 94 95#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ 96#define CONFIG_ETHER_INDEX 1 /* which SCC channel for ethernet */ 97 98#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ 99/* 100 * - Rx-CLK is CLK11 101 * - Tx-CLK is CLK10 102 */ 103#define CONFIG_ETHER_ON_FCC1 104# define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) 105#ifndef CONFIG_DB_CR826_J30x_ON 106# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK10) 107#else 108# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12) 109#endif 110/* 111 * - Rx-CLK is CLK15 112 * - Tx-CLK is CLK14 113 */ 114#define CONFIG_ETHER_ON_FCC2 115# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) 116# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) 117/* 118 * - RAM for BD/Buffers is on the 60x Bus (see 28-13) 119 * - Enable Full Duplex in FSMR 120 */ 121# define CONFIG_SYS_CPMFCR_RAMTYPE 0 122# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) 123 124/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ 125#define CONFIG_8260_CLKIN 64000000 /* in Hz */ 126 127#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) 128#define CONFIG_BAUDRATE 230400 129#else 130#define CONFIG_BAUDRATE 9600 131#endif 132 133#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 134#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 135 136#undef CONFIG_WATCHDOG /* watchdog disabled */ 137 138/* 139 * BOOTP options 140 */ 141#define CONFIG_BOOTP_SUBNETMASK 142#define CONFIG_BOOTP_GATEWAY 143#define CONFIG_BOOTP_HOSTNAME 144#define CONFIG_BOOTP_BOOTPATH 145#define CONFIG_BOOTP_BOOTFILESIZE 146 147 148/* 149 * Command line configuration. 150 */ 151#include <config_cmd_default.h> 152 153#define CONFIG_CMD_BEDBUG 154#define CONFIG_CMD_DATE 155#define CONFIG_CMD_DHCP 156#define CONFIG_CMD_EEPROM 157#define CONFIG_CMD_I2C 158#define CONFIG_CMD_NFS 159#define CONFIG_CMD_SNTP 160 161#ifdef CONFIG_PCI 162#define CONFIG_PCI_INDIRECT_BRIDGE 163#define CONFIG_CMD_PCI 164#endif 165 166/* 167 * Miscellaneous configurable options 168 */ 169#define CONFIG_SYS_LONGHELP /* undef to save memory */ 170#if defined(CONFIG_CMD_KGDB) 171#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 172#else 173#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 174#endif 175#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 176#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 177#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 178 179#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 180#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 181 182#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 183 184#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */ 185 186/* 187 * For booting Linux, the board info and command line data 188 * have to be in the first 8 MB of memory, since this is 189 * the maximum mapped by the Linux kernel during initialization. 190 */ 191#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 192 193/*----------------------------------------------------------------------- 194 * Flash and Boot ROM mapping 195 */ 196#ifdef CONFIG_FLASH_32MB 197#define CONFIG_SYS_FLASH0_BASE 0x40000000 198#define CONFIG_SYS_FLASH0_SIZE 0x02000000 199#else 200#define CONFIG_SYS_FLASH0_BASE 0xFF000000 201#define CONFIG_SYS_FLASH0_SIZE 0x00800000 202#endif 203#define CONFIG_SYS_BOOTROM_BASE 0xFF800000 204#define CONFIG_SYS_BOOTROM_SIZE 0x00080000 205#define CONFIG_SYS_DOC_BASE 0xFF800000 206#define CONFIG_SYS_DOC_SIZE 0x00100000 207 208/* Flash bank size (for preliminary settings) 209 */ 210#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE 211 212/*----------------------------------------------------------------------- 213 * FLASH organization 214 */ 215#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ 216#ifdef CONFIG_FLASH_32MB 217#define CONFIG_SYS_MAX_FLASH_SECT 135 /* max num of sects on one chip */ 218#else 219#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ 220#endif 221#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ 222#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ 223 224#if 0 225/* Start port with environment in flash; switch to EEPROM later */ 226#define CONFIG_ENV_IS_IN_FLASH 1 227#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x40000) 228#define CONFIG_ENV_SIZE 0x40000 229#define CONFIG_ENV_SECT_SIZE 0x40000 230#else 231/* Final version: environment in EEPROM */ 232#define CONFIG_ENV_IS_IN_EEPROM 1 233#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 234#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 235#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 236#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ 237#define CONFIG_ENV_OFFSET 512 238#define CONFIG_ENV_SIZE (2048 - 512) 239#endif 240 241/*----------------------------------------------------------------------- 242 * Hard Reset Configuration Words 243 * 244 * if you change bits in the HRCW, you must also change the CONFIG_SYS_* 245 * defines for the various registers affected by the HRCW e.g. changing 246 * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. 247 */ 248#if defined(CONFIG_BOOT_ROM) 249#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS01 | HRCW_CIP | HRCW_ISB100 | HRCW_BMS) 250#else 251#define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS) 252#endif 253 254/* no slaves so just fill with zeros */ 255#define CONFIG_SYS_HRCW_SLAVE1 0 256#define CONFIG_SYS_HRCW_SLAVE2 0 257#define CONFIG_SYS_HRCW_SLAVE3 0 258#define CONFIG_SYS_HRCW_SLAVE4 0 259#define CONFIG_SYS_HRCW_SLAVE5 0 260#define CONFIG_SYS_HRCW_SLAVE6 0 261#define CONFIG_SYS_HRCW_SLAVE7 0 262 263/*----------------------------------------------------------------------- 264 * Internal Memory Mapped Register 265 */ 266#define CONFIG_SYS_IMMR 0xF0000000 267 268/*----------------------------------------------------------------------- 269 * Definitions for initial stack pointer and data area (in DPRAM) 270 */ 271#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 272#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ 273#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 274#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 275 276/*----------------------------------------------------------------------- 277 * Start addresses for the final memory configuration 278 * (Set up by the startup code) 279 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 280 * 281 * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE, local SDRAM 282 * is mapped at SDRAM_BASE2_PRELIM. 283 */ 284#define CONFIG_SYS_SDRAM_BASE 0x00000000 285#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE 286#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 287#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 288#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ 289 290#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 291# define CONFIG_SYS_RAMBOOT 292#endif 293 294#ifdef CONFIG_PCI 295#define CONFIG_PCI_PNP 296#define CONFIG_EEPRO100 297#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ 298#endif 299 300/*----------------------------------------------------------------------- 301 * Cache Configuration 302 */ 303#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ 304#if defined(CONFIG_CMD_KGDB) 305# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 306#endif 307 308/*----------------------------------------------------------------------- 309 * HIDx - Hardware Implementation-dependent Registers 2-11 310 *----------------------------------------------------------------------- 311 * HID0 also contains cache control - initially enable both caches and 312 * invalidate contents, then the final state leaves only the instruction 313 * cache enabled. Note that Power-On and Hard reset invalidate the caches, 314 * but Soft reset does not. 315 * 316 * HID1 has only read-only information - nothing to set. 317 */ 318#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ 319 HID0_IFEM|HID0_ABE) 320#define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE) 321#define CONFIG_SYS_HID2 0 322 323/*----------------------------------------------------------------------- 324 * RMR - Reset Mode Register 5-5 325 *----------------------------------------------------------------------- 326 * turn on Checkstop Reset Enable 327 */ 328#define CONFIG_SYS_RMR RMR_CSRE 329 330/*----------------------------------------------------------------------- 331 * BCR - Bus Configuration 4-25 332 *----------------------------------------------------------------------- 333 */ 334 335#define BCR_APD01 0x10000000 336#define CONFIG_SYS_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ 337 338/*----------------------------------------------------------------------- 339 * SIUMCR - SIU Module Configuration 4-31 340 *----------------------------------------------------------------------- 341 */ 342#if 0 343#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_CS10PC01) 344#else 345#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10) 346#endif 347 348 349/*----------------------------------------------------------------------- 350 * SYPCR - System Protection Control 4-35 351 * SYPCR can only be written once after reset! 352 *----------------------------------------------------------------------- 353 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable 354 */ 355#if defined(CONFIG_WATCHDOG) 356#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ 357 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) 358#else 359#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ 360 SYPCR_SWRI|SYPCR_SWP) 361#endif /* CONFIG_WATCHDOG */ 362 363/*----------------------------------------------------------------------- 364 * TMCNTSC - Time Counter Status and Control 4-40 365 *----------------------------------------------------------------------- 366 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, 367 * and enable Time Counter 368 */ 369#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) 370 371/*----------------------------------------------------------------------- 372 * PISCR - Periodic Interrupt Status and Control 4-42 373 *----------------------------------------------------------------------- 374 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable 375 * Periodic timer 376 */ 377#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) 378 379/*----------------------------------------------------------------------- 380 * SCCR - System Clock Control 9-8 381 *----------------------------------------------------------------------- 382 */ 383#define CONFIG_SYS_SCCR (SCCR_DFBRG00) 384 385/*----------------------------------------------------------------------- 386 * RCCR - RISC Controller Configuration 13-7 387 *----------------------------------------------------------------------- 388 */ 389#define CONFIG_SYS_RCCR 0 390 391/* 392 * Init Memory Controller: 393 * 394 * Bank Bus Machine PortSz Device 395 * ---- --- ------- ------ ------ 396 * 0 60x GPCM 64 bit FLASH 397 * 1 60x SDRAM 64 bit SDRAM 398 * 399 */ 400 401 /* Initialize SDRAM on local bus 402 */ 403#define CONFIG_SYS_INIT_LOCAL_SDRAM 404 405 406/* Minimum mask to separate preliminary 407 * address ranges for CS[0:2] 408 */ 409#define CONFIG_SYS_MIN_AM_MASK 0xC0000000 410 411/* 412 * we use the same values for 32 MB and 128 MB SDRAM 413 * refresh rate = 7.73 uS (64 MHz Bus Clock) 414 */ 415#define CONFIG_SYS_MPTPR 0x2000 416#define CONFIG_SYS_PSRT 0x0E 417 418#define CONFIG_SYS_MRS_OFFS 0x00000000 419 420 421#if defined(CONFIG_BOOT_ROM) 422/* 423 * Bank 0 - Boot ROM (8 bit wide) 424 */ 425#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\ 426 BRx_PS_8 |\ 427 BRx_MS_GPCM_P |\ 428 BRx_V) 429 430#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE) |\ 431 ORxG_CSNT |\ 432 ORxG_ACS_DIV1 |\ 433 ORxG_SCY_3_CLK |\ 434 ORxG_EHTR |\ 435 ORxG_TRLX) 436 437/* 438 * Bank 1 - Flash (64 bit wide) 439 */ 440#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ 441 BRx_PS_64 |\ 442 BRx_MS_GPCM_P |\ 443 BRx_V) 444 445#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ 446 ORxG_CSNT |\ 447 ORxG_ACS_DIV1 |\ 448 ORxG_SCY_3_CLK |\ 449 ORxG_EHTR |\ 450 ORxG_TRLX) 451 452#else /* ! CONFIG_BOOT_ROM */ 453 454/* 455 * Bank 0 - Flash (64 bit wide) 456 */ 457#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ 458 BRx_PS_64 |\ 459 BRx_MS_GPCM_P |\ 460 BRx_V) 461 462#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ 463 ORxG_CSNT |\ 464 ORxG_ACS_DIV1 |\ 465 ORxG_SCY_3_CLK |\ 466 ORxG_EHTR |\ 467 ORxG_TRLX) 468 469/* 470 * Bank 1 - Disk-On-Chip 471 */ 472#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_DOC_BASE & BRx_BA_MSK) |\ 473 BRx_PS_8 |\ 474 BRx_MS_GPCM_P |\ 475 BRx_V) 476 477#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_DOC_SIZE) |\ 478 ORxG_CSNT |\ 479 ORxG_ACS_DIV1 |\ 480 ORxG_SCY_3_CLK |\ 481 ORxG_EHTR |\ 482 ORxG_TRLX) 483 484#endif /* CONFIG_BOOT_ROM */ 485 486/* Bank 2 - SDRAM 487 */ 488 489#ifndef CONFIG_SYS_RAMBOOT 490#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ 491 BRx_PS_64 |\ 492 BRx_MS_SDRAM_P |\ 493 BRx_V) 494 495 /* SDRAM initialization values for 8-column chips 496 */ 497#define CONFIG_SYS_OR2_8COL (CONFIG_SYS_MIN_AM_MASK |\ 498 ORxS_BPD_4 |\ 499 ORxS_ROWST_PBI0_A9 |\ 500 ORxS_NUMR_12) 501 502#define CONFIG_SYS_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\ 503 PSDMR_BSMA_A14_A16 |\ 504 PSDMR_SDA10_PBI0_A10 |\ 505 PSDMR_RFRC_7_CLK |\ 506 PSDMR_PRETOACT_2W |\ 507 PSDMR_ACTTORW_1W |\ 508 PSDMR_LDOTOPRE_1C |\ 509 PSDMR_WRC_1C |\ 510 PSDMR_CL_2) 511 512 /* SDRAM initialization values for 9-column chips 513 */ 514#define CONFIG_SYS_OR2_9COL (CONFIG_SYS_MIN_AM_MASK |\ 515 ORxS_BPD_4 |\ 516 ORxS_ROWST_PBI0_A7 |\ 517 ORxS_NUMR_13) 518 519#define CONFIG_SYS_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\ 520 PSDMR_BSMA_A13_A15 |\ 521 PSDMR_SDA10_PBI0_A9 |\ 522 PSDMR_RFRC_7_CLK |\ 523 PSDMR_PRETOACT_2W |\ 524 PSDMR_ACTTORW_1W |\ 525 PSDMR_LDOTOPRE_1C |\ 526 PSDMR_WRC_1C |\ 527 PSDMR_CL_2) 528 529#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2_9COL 530#define CONFIG_SYS_PSDMR CONFIG_SYS_PSDMR_9COL 531 532#endif /* CONFIG_SYS_RAMBOOT */ 533 534#endif /* __CONFIG_H */ 535