uboot/include/configs/csb272.h
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   1/*
   2 * (C) Copyright 2004
   3 * Tolunay Orkun, Nextio Inc., torkun@nextio.com
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 */
   7
   8/*
   9 * board/config.h - configuration options, board specific
  10 */
  11
  12#ifndef __CONFIG_H
  13#define __CONFIG_H
  14
  15/*
  16 * High Level Configuration Options
  17 * (easy to change)
  18 */
  19
  20#define CONFIG_405GP            1       /* This is a PPC405GP CPU       */
  21#define CONFIG_CSB272           1       /* on a Cogent CSB272 board     */
  22#define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f()    */
  23#define CONFIG_LAST_STAGE_INIT  1       /* Call last_stage_init()       */
  24#define CONFIG_SYS_CLK_FREQ     33000000 /* external frequency to pll   */
  25
  26#define CONFIG_SYS_TEXT_BASE    0xFFFC0000
  27
  28/*
  29 * OS Bootstrap configuration
  30 *
  31 */
  32
  33#if 0
  34#define CONFIG_BOOTDELAY        -1      /* autoboot disabled */
  35#else
  36#define CONFIG_BOOTDELAY        3       /* autoboot after X seconds     */
  37#endif
  38
  39#define CONFIG_ZERO_BOOTDELAY_CHECK     /* check keypress when bootdelay = 0 */
  40
  41#if 1
  42#undef  CONFIG_BOOTARGS
  43#define CONFIG_BOOTCOMMAND \
  44        "setenv bootargs console=ttyS0,38400 debug " \
  45        "root=/dev/ram rw ramdisk_size=4096 " \
  46        "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
  47        "bootm fe000000 fe100000"
  48#endif
  49
  50#if 0
  51#undef  CONFIG_BOOTARGS
  52#define CONFIG_BOOTCOMMAND \
  53        "bootp; " \
  54        "setenv bootargs console=ttyS0,38400 debug " \
  55        "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
  56        "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
  57        "bootm"
  58#endif
  59
  60/*
  61 * BOOTP options
  62 */
  63#define CONFIG_BOOTP_SUBNETMASK
  64#define CONFIG_BOOTP_GATEWAY
  65#define CONFIG_BOOTP_HOSTNAME
  66#define CONFIG_BOOTP_BOOTPATH
  67#define CONFIG_BOOTP_BOOTFILESIZE
  68#define CONFIG_BOOTP_DNS2
  69
  70
  71/*
  72 * Command line configuration.
  73 */
  74#include <config_cmd_default.h>
  75
  76#define CONFIG_CMD_ASKENV
  77#define CONFIG_CMD_BEDBUG
  78#define CONFIG_CMD_ELF
  79#define CONFIG_CMD_IRQ
  80#define CONFIG_CMD_I2C
  81#define CONFIG_CMD_PCI
  82#define CONFIG_CMD_DATE
  83#define CONFIG_CMD_MII
  84#define CONFIG_CMD_PING
  85#define CONFIG_CMD_DHCP
  86
  87
  88/*
  89 * Serial download configuration
  90 *
  91 */
  92#define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  93#define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
  94
  95/*
  96 * KGDB Configuration
  97 *
  98 */
  99#if defined(CONFIG_CMD_KGDB)
 100#define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 101#endif
 102
 103/*
 104 * Miscellaneous configurable options
 105 *
 106 */
 107#undef  CONFIG_SYS_HUSH_PARSER                  /* use "hush" command parser */
 108
 109#define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 110#if defined(CONFIG_CMD_KGDB)
 111#define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size */
 112#else
 113#define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
 114#endif
 115#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 116#define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 117#define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 118
 119#define CONFIG_SYS_MEMTEST_START        0x0400000 /* memtest works on */
 120#define CONFIG_SYS_MEMTEST_END          0x0C00000 /* 4 ... 12 MB in DRAM */
 121#define CONFIG_SYS_EXTBDINFO            1       /* To use extended board_info (bd_t) */
 122#define CONFIG_SYS_LOAD_ADDR            0x100000 /* default load address */
 123
 124/*
 125 * For booting Linux, the board info and command line data
 126 * have to be in the first 8 MB of memory, since this is
 127 * the maximum mapped by the Linux kernel during initialization.
 128 */
 129#define CONFIG_SYS_BOOTMAPSZ            (8 << 20) /* Initial Memory map for Linux */
 130
 131/*
 132 * watchdog configuration
 133 *
 134 */
 135#undef  CONFIG_WATCHDOG                 /* watchdog disabled */
 136
 137/*
 138 * UART configuration
 139 *
 140 */
 141#define CONFIG_CONS_INDEX               1       /* Use UART0            */
 142#define CONFIG_SYS_NS16550
 143#define CONFIG_SYS_NS16550_SERIAL
 144#define CONFIG_SYS_NS16550_REG_SIZE     1
 145#define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 146
 147#define CONFIG_SYS_EXT_SERIAL_CLOCK     3868400 /* use external serial clock */
 148#undef  CONFIG_SYS_BASE_BAUD
 149#define CONFIG_BAUDRATE         38400   /* Default baud rate */
 150#define CONFIG_SYS_BAUDRATE_TABLE      \
 151    { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400 }
 152
 153/*
 154 * I2C configuration
 155 *
 156 */
 157#define CONFIG_SYS_I2C
 158#define CONFIG_SYS_I2C_PPC4XX
 159#define CONFIG_SYS_I2C_PPC4XX_CH0
 160#define CONFIG_SYS_I2C_PPC4XX_SPEED_0           100000
 161#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F    /* I2C slave address */
 162
 163/*
 164 * MII PHY configuration
 165 *
 166 */
 167#define CONFIG_PPC4xx_EMAC
 168#define CONFIG_MII              1       /* MII PHY management           */
 169#define CONFIG_PHY_ADDR         0       /* PHY address                  */
 170#define CONFIG_PHY_CMD_DELAY    40      /* PHY COMMAND delay            */
 171                                        /* 32usec min. for LXT971A      */
 172#define CONFIG_PHY_RESET_DELAY  300     /* PHY RESET recovery delay     */
 173
 174/*
 175 * RTC configuration
 176 *
 177 * Note that DS1307 RTC is limited to 100Khz I2C bus.
 178 *
 179 */
 180#define CONFIG_RTC_DS1307               /* Use Dallas 1307 RTC          */
 181
 182/*
 183 * PCI stuff
 184 *
 185 */
 186#define CONFIG_PCI                      /* include pci support          */
 187#define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 188#define PCI_HOST_ADAPTER        0       /* configure ar pci adapter     */
 189#define PCI_HOST_FORCE          1       /* configure as pci host        */
 190#define PCI_HOST_AUTO           2       /* detected via arbiter enable  */
 191
 192#define CONFIG_PCI_HOST PCI_HOST_FORCE  /* select pci host function     */
 193#define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 194                                        /* resource configuration       */
 195#undef  CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 196#define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
 197
 198#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000  /* PCI Vendor ID: to-do!!!      */
 199#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000  /* PCI Device ID: to-do!!!      */
 200#define CONFIG_SYS_PCI_PTM1LA  0x00000000      /* point to sdram               */
 201#define CONFIG_SYS_PCI_PTM1MS  0x80000001      /* 2GB, enable hard-wired to 1  */
 202#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 203#define CONFIG_SYS_PCI_PTM2LA  0x00000000      /* disabled                     */
 204#define CONFIG_SYS_PCI_PTM2MS  0x00000000      /* disabled                     */
 205#define CONFIG_SYS_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
 206
 207/*
 208 * IDE stuff
 209 *
 210 */
 211#undef  CONFIG_IDE_PCMCIA               /* no pcmcia interface required */
 212#undef  CONFIG_IDE_LED                  /* no led for ide supported     */
 213#undef  CONFIG_IDE_RESET                /* no reset for ide supported   */
 214
 215/*
 216 * Environment configuration
 217 *
 218 */
 219#define CONFIG_ENV_IS_IN_FLASH  1       /* environment is in FLASH      */
 220#undef CONFIG_ENV_IS_IN_NVRAM
 221#undef CONFIG_ENV_IS_IN_EEPROM
 222
 223/*
 224 * General Memory organization
 225 *
 226 * Start addresses for the final memory configuration
 227 * (Set up by the startup code)
 228 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 229 */
 230#define CONFIG_SYS_SDRAM_BASE           0x00000000
 231#define CONFIG_SYS_FLASH_BASE           0xFE000000
 232#define CONFIG_SYS_FLASH_SIZE           0x02000000
 233#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 234#define CONFIG_SYS_MONITOR_LEN          (256 * 1024) /* Reserve 256 KB for Monitor */
 235#define CONFIG_SYS_MALLOC_LEN           (128 * 1024) /* Reserve 128 KB for malloc() */
 236
 237#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE
 238#define CONFIG_SYS_RAMSTART
 239#endif
 240
 241#if defined(CONFIG_ENV_IS_IN_FLASH)
 242#define CONFIG_ENV_IN_OWN_SECTOR        1          /* Give Environment own sector */
 243#define CONFIG_ENV_ADDR         0xFFF00000 /* Address of Environment Sector */
 244#define CONFIG_ENV_SIZE         0x00001000 /* Size of Environment */
 245#define CONFIG_ENV_SECT_SIZE    0x00040000 /* Size of Environment Sector */
 246#endif
 247
 248/*
 249 * FLASH Device configuration
 250 *
 251 */
 252#define CONFIG_SYS_FLASH_CFI            1       /* flash is CFI conformant      */
 253#define CONFIG_FLASH_CFI_DRIVER 1       /* use common cfi driver        */
 254#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster) */
 255#define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max # of memory banks        */
 256#define CONFIG_SYS_FLASH_INCREMENT      0       /* there is only one bank       */
 257#define CONFIG_SYS_MAX_FLASH_SECT       128     /* max # of sectors on one chip */
 258#define CONFIG_SYS_FLASH_PROTECTION     1       /* hardware flash protection    */
 259#define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 260
 261/*
 262 * On Chip Memory location/size
 263 *
 264 */
 265#define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 266#define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 267
 268/*
 269 * Global info and initial stack
 270 *
 271 */
 272#define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* inside of on-chip SRAM */
 273#define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
 274#define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 275#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 276
 277/*
 278 * Miscellaneous board specific definitions
 279 *
 280 */
 281#define CONFIG_SYS_I2C_PLL_ADDR 0x58    /* I2C address of AMIS FS6377-01 PLL */
 282#define CONFIG_I2CFAST          1       /* enable "i2cfast" env. setting     */
 283
 284#endif  /* __CONFIG_H */
 285
Hosted by Missing Link Electronics. The original LXR software by the LXR community, this experimental version by lxr@linux.no.