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15#ifndef __CONFIG_H
16#define __CONFIG_H
17
18
19
20
21#define CONFIG_KILAUEA 1
22#define CONFIG_405EX 1
23#define CONFIG_SYS_CLK_FREQ 33333333
24
25#ifndef CONFIG_SYS_TEXT_BASE
26#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
27#endif
28
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44
45
46#define CONFIG_HOSTNAME kilauea
47#include "amcc-common.h"
48
49#define CONFIG_BOARD_EARLY_INIT_F 1
50#define CONFIG_MISC_INIT_R 1
51#define CONFIG_BOARD_TYPES
52#define CONFIG_BOARD_EMAC_COUNT
53
54
55
56
57
58#define CONFIG_SYS_FLASH_BASE 0xFC000000
59#define CONFIG_SYS_NAND_ADDR 0xF8000000
60#define CONFIG_SYS_FPGA_BASE 0xF0000000
61
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83
84#define CONFIG_SYS_INIT_DCACHE_CS 4
85
86#if defined(CONFIG_SYS_INIT_DCACHE_CS)
87#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_SDRAM_BASE + ( 1 << 30))
88#else
89#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_SDRAM_BASE + (32 << 20))
90#endif
91
92#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
93#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
94
95
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99
100
101
102
103#if defined(CONFIG_SYS_INIT_DCACHE_CS)
104# define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
105# define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
106#else
107# define CONFIG_SYS_INIT_EXTRA_SIZE 16
108# define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_EXTRA_SIZE)
109# define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_INIT_RAM_ADDR
110#endif
111
112
113
114
115#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200
116#define CONFIG_CONS_INDEX 1
117
118
119
120
121#define CONFIG_ENV_IS_IN_FLASH 1
122
123
124
125
126#define CONFIG_SYS_FLASH_CFI
127#define CONFIG_FLASH_CFI_DRIVER
128
129#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
130#define CONFIG_SYS_MAX_FLASH_BANKS 1
131#define CONFIG_SYS_MAX_FLASH_SECT 512
132
133#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
134#define CONFIG_SYS_FLASH_WRITE_TOUT 500
135
136#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
137#define CONFIG_SYS_FLASH_EMPTY_INFO
138
139#ifdef CONFIG_ENV_IS_IN_FLASH
140#define CONFIG_ENV_SECT_SIZE 0x20000
141#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
142#define CONFIG_ENV_SIZE 0x4000
143
144
145#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
146#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
147#endif
148
149
150
151
152#define CONFIG_SYS_MAX_NAND_DEVICE 1
153#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
154#define CONFIG_SYS_NAND_SELECT_DEVICE 1
155
156
157
158
159#define CONFIG_SYS_MBYTES_SDRAM (256)
160
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170
171
172
173#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION
174#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION
175#undef CONFIG_PPC4xx_DDR_METHOD_A
176
177#define CONFIG_SYS_SDRAM0_MB0CF_BASE (( 0 << 20) + CONFIG_SYS_SDRAM_BASE)
178
179
180#define CONFIG_SYS_SDRAM0_MB0CF ((CONFIG_SYS_SDRAM0_MB0CF_BASE >> 3) | \
181 SDRAM_RXBAS_SDSZ_256MB | \
182 SDRAM_RXBAS_SDAM_MODE7 | \
183 SDRAM_RXBAS_SDBE_ENABLE)
184#define CONFIG_SYS_SDRAM0_MB1CF SDRAM_RXBAS_SDBE_DISABLE
185#define CONFIG_SYS_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE
186#define CONFIG_SYS_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE
187#define CONFIG_SYS_SDRAM0_MCOPT1 (SDRAM_MCOPT1_PMU_OPEN | \
188 SDRAM_MCOPT1_8_BANKS | \
189 SDRAM_MCOPT1_DDR2_TYPE | \
190 SDRAM_MCOPT1_QDEP | \
191 SDRAM_MCOPT1_DCOO_DISABLED)
192#define CONFIG_SYS_SDRAM0_MCOPT2 0x00000000
193#define CONFIG_SYS_SDRAM0_MODT0 (SDRAM_MODT_EB0W_ENABLE | \
194 SDRAM_MODT_EB0R_ENABLE)
195#define CONFIG_SYS_SDRAM0_MODT1 0x00000000
196#define CONFIG_SYS_SDRAM0_CODT (SDRAM_CODT_RK0R_ON | \
197 SDRAM_CODT_CKLZ_36OHM | \
198 SDRAM_CODT_DQS_1_8_V_DDR2 | \
199 SDRAM_CODT_IO_NMODE)
200#define CONFIG_SYS_SDRAM0_RTR SDRAM_RTR_RINT_ENCODE(1560)
201#define CONFIG_SYS_SDRAM0_INITPLR0 (SDRAM_INITPLR_ENABLE | \
202 SDRAM_INITPLR_IMWT_ENCODE(80) | \
203 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP))
204#define CONFIG_SYS_SDRAM0_INITPLR1 (SDRAM_INITPLR_ENABLE | \
205 SDRAM_INITPLR_IMWT_ENCODE(3) | \
206 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \
207 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
208 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
209#define CONFIG_SYS_SDRAM0_INITPLR2 (SDRAM_INITPLR_ENABLE | \
210 SDRAM_INITPLR_IMWT_ENCODE(2) | \
211 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
212 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2) | \
213 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL))
214#define CONFIG_SYS_SDRAM0_INITPLR3 (SDRAM_INITPLR_ENABLE | \
215 SDRAM_INITPLR_IMWT_ENCODE(2) | \
216 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
217 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3) | \
218 SDRAM_INITPLR_IMA_ENCODE(0))
219#define CONFIG_SYS_SDRAM0_INITPLR4 (SDRAM_INITPLR_ENABLE | \
220 SDRAM_INITPLR_IMWT_ENCODE(2) | \
221 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
222 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
223 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_DISABLE | \
224 JEDEC_MA_EMR_RTT_75OHM))
225#define CONFIG_SYS_SDRAM0_INITPLR5 (SDRAM_INITPLR_ENABLE | \
226 SDRAM_INITPLR_IMWT_ENCODE(2) | \
227 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
228 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
229 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
230 JEDEC_MA_MR_CL_DDR2_4_0_CLK | \
231 JEDEC_MA_MR_BLEN_4 | \
232 JEDEC_MA_MR_DLL_RESET))
233#define CONFIG_SYS_SDRAM0_INITPLR6 (SDRAM_INITPLR_ENABLE | \
234 SDRAM_INITPLR_IMWT_ENCODE(3) | \
235 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \
236 SDRAM_INITPLR_IBA_ENCODE(0x0) | \
237 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
238#define CONFIG_SYS_SDRAM0_INITPLR7 (SDRAM_INITPLR_ENABLE | \
239 SDRAM_INITPLR_IMWT_ENCODE(26) | \
240 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
241#define CONFIG_SYS_SDRAM0_INITPLR8 (SDRAM_INITPLR_ENABLE | \
242 SDRAM_INITPLR_IMWT_ENCODE(26) | \
243 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
244#define CONFIG_SYS_SDRAM0_INITPLR9 (SDRAM_INITPLR_ENABLE | \
245 SDRAM_INITPLR_IMWT_ENCODE(26) | \
246 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
247#define CONFIG_SYS_SDRAM0_INITPLR10 (SDRAM_INITPLR_ENABLE | \
248 SDRAM_INITPLR_IMWT_ENCODE(26) | \
249 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
250#define CONFIG_SYS_SDRAM0_INITPLR11 (SDRAM_INITPLR_ENABLE | \
251 SDRAM_INITPLR_IMWT_ENCODE(2) | \
252 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
253 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
254 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
255 JEDEC_MA_MR_CL_DDR2_4_0_CLK | \
256 JEDEC_MA_MR_BLEN_4))
257#define CONFIG_SYS_SDRAM0_INITPLR12 (SDRAM_INITPLR_ENABLE | \
258 SDRAM_INITPLR_IMWT_ENCODE(2) | \
259 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
260 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
261 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_ENTER | \
262 JEDEC_MA_EMR_RDQS_DISABLE | \
263 JEDEC_MA_EMR_DQS_DISABLE | \
264 JEDEC_MA_EMR_RTT_DISABLED | \
265 JEDEC_MA_EMR_ODS_NORMAL))
266#define CONFIG_SYS_SDRAM0_INITPLR13 (SDRAM_INITPLR_ENABLE | \
267 SDRAM_INITPLR_IMWT_ENCODE(2) | \
268 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
269 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
270 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_EXIT | \
271 JEDEC_MA_EMR_RDQS_DISABLE | \
272 JEDEC_MA_EMR_DQS_DISABLE | \
273 JEDEC_MA_EMR_RTT_DISABLED | \
274 JEDEC_MA_EMR_ODS_NORMAL))
275#define CONFIG_SYS_SDRAM0_INITPLR14 (SDRAM_INITPLR_DISABLE)
276#define CONFIG_SYS_SDRAM0_INITPLR15 (SDRAM_INITPLR_DISABLE)
277#define CONFIG_SYS_SDRAM0_RQDC (SDRAM_RQDC_RQDE_ENABLE | \
278 SDRAM_RQDC_RQFD_ENCODE(56))
279#define CONFIG_SYS_SDRAM0_RFDC SDRAM_RFDC_RFFD_ENCODE(521)
280#define CONFIG_SYS_SDRAM0_RDCC (SDRAM_RDCC_RDSS_T2)
281#define CONFIG_SYS_SDRAM0_DLCR (SDRAM_DLCR_DCLM_AUTO | \
282 SDRAM_DLCR_DLCS_CONT_DONE | \
283 SDRAM_DLCR_DLCV_ENCODE(165))
284#define CONFIG_SYS_SDRAM0_CLKTR (SDRAM_CLKTR_CLKP_180_DEG_ADV)
285#define CONFIG_SYS_SDRAM0_WRDTR 0x00000000
286#define CONFIG_SYS_SDRAM0_SDTR1 (SDRAM_SDTR1_LDOF_2_CLK | \
287 SDRAM_SDTR1_RTW_2_CLK | \
288 SDRAM_SDTR1_RTRO_1_CLK)
289#define CONFIG_SYS_SDRAM0_SDTR2 (SDRAM_SDTR2_RCD_3_CLK | \
290 SDRAM_SDTR2_WTR_2_CLK | \
291 SDRAM_SDTR2_XSNR_32_CLK | \
292 SDRAM_SDTR2_WPC_4_CLK | \
293 SDRAM_SDTR2_RPC_2_CLK | \
294 SDRAM_SDTR2_RP_3_CLK | \
295 SDRAM_SDTR2_RRD_2_CLK)
296#define CONFIG_SYS_SDRAM0_SDTR3 (SDRAM_SDTR3_RAS_ENCODE(8) | \
297 SDRAM_SDTR3_RC_ENCODE(11) | \
298 SDRAM_SDTR3_XCS | \
299 SDRAM_SDTR3_RFC_ENCODE(26))
300#define CONFIG_SYS_SDRAM0_MMODE (SDRAM_MMODE_WR_DDR2_3_CYC | \
301 SDRAM_MMODE_DCL_DDR2_4_0_CLK | \
302 SDRAM_MMODE_BLEN_4)
303#define CONFIG_SYS_SDRAM0_MEMODE (SDRAM_MEMODE_DQS_DISABLE | \
304 SDRAM_MEMODE_RTT_75OHM)
305
306
307
308
309#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
310
311#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
312#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
313#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
314#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
315
316
317#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52
318#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
319#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
320
321
322#define CONFIG_DTT_DS1775 1
323#define CONFIG_DTT_SENSORS { 0 }
324#define CONFIG_SYS_I2C_DTT_ADDR 0x48
325
326
327#define CONFIG_RTC_DS1338 1
328#define CONFIG_SYS_I2C_RTC_ADDR 0x68
329
330
331
332
333#define CONFIG_M88E1111_PHY 1
334#define CONFIG_IBM_EMAC4_V4 1
335#define CONFIG_EMAC_PHY_MODE EMAC_PHY_MODE_RGMII_RGMII
336#define CONFIG_PHY_ADDR 1
337
338#define CONFIG_PHY_RESET 1
339#define CONFIG_PHY_GIGE 1
340
341#define CONFIG_HAS_ETH0 1
342
343#define CONFIG_HAS_ETH1 1
344#define CONFIG_PHY1_ADDR 2
345
346
347#define CONFIG_AUTOCALIB "silent\0"
348
349
350
351
352#define CONFIG_EXTRA_ENV_SETTINGS \
353 CONFIG_AMCC_DEF_ENV \
354 CONFIG_AMCC_DEF_ENV_POWERPC \
355 CONFIG_AMCC_DEF_ENV_PPC_OLD \
356 CONFIG_AMCC_DEF_ENV_NOR_UPD \
357 "logversion=2\0" \
358 "kernel_addr=fc000000\0" \
359 "fdt_addr=fc1e0000\0" \
360 "ramdisk_addr=fc200000\0" \
361 "pciconfighost=1\0" \
362 "pcie_mode=RP:RP\0" \
363 ""
364
365
366
367
368#define CONFIG_CMD_CHIP_CONFIG
369#define CONFIG_CMD_DATE
370#define CONFIG_CMD_NAND
371#define CONFIG_CMD_PCI
372#define CONFIG_CMD_SNTP
373
374#define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY
375
376
377#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
378 CONFIG_SYS_POST_CPU | \
379 CONFIG_SYS_POST_ETHER | \
380 CONFIG_SYS_POST_I2C | \
381 CONFIG_SYS_POST_MEMORY_ON | \
382 CONFIG_SYS_POST_UART)
383
384
385#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \
386 CONFIG_SYS_NS16550_COM2 }
387
388#define CONFIG_LOGBUFFER
389#define CONFIG_SYS_POST_CACHE_ADDR 0x00800000
390
391#define CONFIG_SYS_CONSOLE_IS_IN_ENV
392
393
394
395
396#define CONFIG_PCI
397#define CONFIG_PCI_INDIRECT_BRIDGE
398#define CONFIG_PCI_PNP 1
399#define CONFIG_PCI_SCAN_SHOW 1
400#define CONFIG_PCI_CONFIG_HOST_BRIDGE
401
402
403
404
405#define CONFIG_SYS_PCIE_MEMBASE 0x90000000
406#define CONFIG_SYS_PCIE_MEMSIZE 0x08000000
407
408#define CONFIG_SYS_PCIE0_CFGBASE 0xa0000000
409#define CONFIG_SYS_PCIE0_XCFGBASE 0xb0000000
410#define CONFIG_SYS_PCIE0_CFGMASK 0xe0000001
411
412#define CONFIG_SYS_PCIE1_CFGBASE 0xc0000000
413#define CONFIG_SYS_PCIE1_XCFGBASE 0xd0000000
414#define CONFIG_SYS_PCIE1_CFGMASK 0xe0000001
415
416#define CONFIG_SYS_PCIE0_UTLBASE 0xef502000
417#define CONFIG_SYS_PCIE1_UTLBASE 0xef503000
418
419
420#define CONFIG_SYS_PCIE_INBOUND_BASE 0x0000000000000000ULL
421
422
423
424
425#define CONFIG_SYS_NAND_CS 1
426
427
428#define CONFIG_SYS_EBC_PB0AP 0x05806500
429#define CONFIG_SYS_EBC_PB0CR 0xFC0DA000
430
431
432#define CONFIG_SYS_EBC_PB1AP 0x018003c0
433#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_NAND_ADDR | 0x1e000)
434
435
436#define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_ENABLED | \
437 EBC_BXAP_FWT_ENCODE(6) | \
438 EBC_BXAP_BWT_ENCODE(1) | \
439 EBC_BXAP_BCE_DISABLE | \
440 EBC_BXAP_BCT_2TRANS | \
441 EBC_BXAP_CSN_ENCODE(0) | \
442 EBC_BXAP_OEN_ENCODE(0) | \
443 EBC_BXAP_WBN_ENCODE(3) | \
444 EBC_BXAP_WBF_ENCODE(1) | \
445 EBC_BXAP_TH_ENCODE(4) | \
446 EBC_BXAP_RE_DISABLED | \
447 EBC_BXAP_SOR_DELAYED | \
448 EBC_BXAP_BEM_WRITEONLY | \
449 EBC_BXAP_PEN_DISABLED)
450#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA_BASE | 0x18000)
451
452#define CONFIG_SYS_EBC_CFG 0x7FC00000
453
454
455
456
457#define CONFIG_SYS_4xx_GPIO_TABLE { \
458{ \
459 \
460{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, \
461{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, \
462{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, \
463{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, \
464{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, \
465{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, \
466{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, \
467{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, \
468{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
469{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
470{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
471{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, \
472{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, \
473{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, \
474{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, \
475{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, \
476{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, \
477{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, \
478{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, \
479{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
480{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, \
481{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0}, \
482{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, \
483{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, \
484{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, \
485{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, \
486{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
487{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, \
488{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, \
489{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0}, \
490{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, \
491{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, \
492} \
493}
494
495
496
497
498#define CONFIG_SYS_FPGA_REG_BASE CONFIG_SYS_FPGA_BASE
499#define CONFIG_SYS_FPGA_FIFO_BASE (CONFIG_SYS_FPGA_BASE | (1 << 10))
500
501
502#define CONFIG_SYS_FPGA_SLIC0_R_DPRAM_INT 0x80000000
503#define CONFIG_SYS_FPGA_SLIC0_W_DPRAM_INT 0x40000000
504#define CONFIG_SYS_FPGA_SLIC1_R_DPRAM_INT 0x20000000
505#define CONFIG_SYS_FPGA_SLIC1_W_DPRAM_INT 0x10000000
506#define CONFIG_SYS_FPGA_PHY0_INT 0x08000000
507#define CONFIG_SYS_FPGA_PHY1_INT 0x04000000
508#define CONFIG_SYS_FPGA_SLIC0_INT 0x02000000
509#define CONFIG_SYS_FPGA_SLIC1_INT 0x01000000
510
511
512
513#define CONFIG_SYS_FPGA_DPRAM_R_INT_LINE 0x00400000
514#define CONFIG_SYS_FPGA_DPRAM_W_INT_LINE 0x00100000
515#define CONFIG_SYS_FPGA_DPRAM_RW_TYPE 0x00080000
516#define CONFIG_SYS_FPGA_DPRAM_RST 0x00040000
517#define CONFIG_SYS_FPGA_UART0_FO 0x00020000
518#define CONFIG_SYS_FPGA_UART1_FO 0x00010000
519
520
521#define CONFIG_SYS_FPGA_CHIPSIDE_LOOPBACK 0x00004000
522#define CONFIG_SYS_FPGA_LINESIDE_LOOPBACK 0x00008000
523#define CONFIG_SYS_FPGA_SLIC0_ENABLE 0x00002000
524#define CONFIG_SYS_FPGA_SLIC1_ENABLE 0x00001000
525#define CONFIG_SYS_FPGA_SLIC0_CS 0x00000800
526#define CONFIG_SYS_FPGA_SLIC1_CS 0x00000400
527#define CONFIG_SYS_FPGA_USER_LED0 0x00000200
528#define CONFIG_SYS_FPGA_USER_LED1 0x00000100
529
530#define CONFIG_SYS_FPGA_MAGIC_MASK 0xffff0000
531#define CONFIG_SYS_FPGA_MAGIC 0xabcd0000
532#define CONFIG_SYS_FPGA_VER_MASK 0x0000ff00
533
534#endif
535