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8#ifndef __CONFIG_H
9#define __CONFIG_H
10
11
12#define CONFIG_405EP 1
13#define CONFIG_NEO 1
14
15#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
16
17
18
19
20#define CONFIG_HOSTNAME neo
21#define CONFIG_IDENT_STRING " neo 0.02"
22#include "amcc-common.h"
23
24#define CONFIG_BOARD_EARLY_INIT_F
25#define CONFIG_BOARD_EARLY_INIT_R
26#define CONFIG_MISC_INIT_R
27#define CONFIG_LAST_STAGE_INIT
28
29#define CONFIG_SYS_CLK_FREQ 33333333
30
31
32
33
34#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
35#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
36
37
38#define CONFIG_FIT
39#define CONFIG_FIT_VERBOSE
40
41#define CONFIG_ENV_IS_IN_FLASH
42
43
44
45
46#define CONFIG_EXTRA_ENV_SETTINGS \
47 CONFIG_AMCC_DEF_ENV \
48 CONFIG_AMCC_DEF_ENV_POWERPC \
49 CONFIG_AMCC_DEF_ENV_NOR_UPD \
50 "kernel_addr=fc000000\0" \
51 "fdt_addr=fc1e0000\0" \
52 "ramdisk_addr=fc200000\0" \
53 ""
54
55#define CONFIG_PHY_ADDR 4
56#define CONFIG_HAS_ETH0
57#define CONFIG_HAS_ETH1
58#define CONFIG_PHY1_ADDR 0xc
59#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
60
61
62
63
64#define CONFIG_CMD_CACHE
65#define CONFIG_CMD_DATE
66#define CONFIG_CMD_DTT
67#undef CONFIG_CMD_EEPROM
68
69
70
71
72#define CONFIG_SDRAM_BANK0 1
73
74
75#define CONFIG_SYS_SDRAM_CL 3
76#define CONFIG_SYS_SDRAM_tRP 20
77#define CONFIG_SYS_SDRAM_tRC 66
78#define CONFIG_SYS_SDRAM_tRCD 20
79#define CONFIG_SYS_SDRAM_tRFC 66
80
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87
88
89
90#define CONFIG_CONS_INDEX 1
91#define CONFIG_SYS_NS16550
92#define CONFIG_SYS_NS16550_SERIAL
93#define CONFIG_SYS_NS16550_REG_SIZE 1
94#define CONFIG_SYS_NS16550_CLK get_serial_clock()
95
96#undef CONFIG_SYS_EXT_SERIAL_CLOCK
97#undef CONFIG_SYS_405_UART_ERRATA_59
98#define CONFIG_SYS_BASE_BAUD 691200
99
100
101
102
103#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
104
105
106#define CONFIG_RTC_DS1337
107#define CONFIG_SYS_I2C_RTC_ADDR 0x68
108
109
110#define CONFIG_DTT_LM63 1
111#define CONFIG_DTT_SENSORS { 0 }
112#define CONFIG_DTT_PWM_LOOKUPTABLE \
113 { { 40, 10 }, { 50, 20 }, { 60, 40 } }
114#define CONFIG_DTT_TACH_LIMIT 0xa10
115
116
117
118
119#define CONFIG_SYS_FLASH_CFI
120#define CONFIG_FLASH_CFI_DRIVER
121
122#define CONFIG_SYS_FLASH_BASE 0xFC000000
123#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
124
125#define CONFIG_SYS_MAX_FLASH_BANKS 1
126#define CONFIG_SYS_MAX_FLASH_SECT 512
127
128#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
129#define CONFIG_SYS_FLASH_WRITE_TOUT 500
130
131#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
132
133#define CONFIG_SYS_FLASH_EMPTY_INFO
134#define CONFIG_SYS_FLASH_QUIET_TEST 1
135
136#ifdef CONFIG_ENV_IS_IN_FLASH
137#define CONFIG_ENV_SECT_SIZE 0x20000
138#define CONFIG_ENV_ADDR 0xFFF00000
139#define CONFIG_ENV_SIZE 0x20000
140
141
142#define CONFIG_ENV_ADDR_REDUND 0xFFF20000
143#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
144#endif
145
146
147
148
149#define CONFIG_SYS_4xx_GPIO_TABLE { \
150{ \
151 \
152{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
153{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
154{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
155{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
156{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
157{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, \
158{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
159{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
160{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
161{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
162{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
163{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
164{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
165{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
166{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
167{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
168{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
169{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
170{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
171{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
172{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
173{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
174{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
175{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
176{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
177{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
178{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
179{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
180{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
181{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
182{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
183{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
184} \
185}
186
187
188
189
190
191#define CONFIG_SYS_TEMP_STACK_OCM 1
192
193
194#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
195#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
196#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR
197#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE
198
199#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
200#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
201
202
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205
206
207#define CONFIG_SYS_EBC_PB0AP 0x92015480
208#define CONFIG_SYS_EBC_PB0CR 0xFC0DA000
209
210
211#define CONFIG_SYS_EBC_PB1AP 0x92015480
212#define CONFIG_SYS_EBC_PB1CR 0xFB85A000
213
214
215#define CONFIG_SYS_FPGA0_BASE 0x7f100000
216#define CONFIG_SYS_EBC_PB2AP 0x92015480
217#define CONFIG_SYS_EBC_PB2CR 0x7f11a000
218
219#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
220
221#define CONFIG_SYS_FPGA_COUNT 1
222
223#define CONFIG_SYS_FPGA_PTR \
224 { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE }
225
226#define CONFIG_SYS_FPGA_COMMON
227
228
229#define CONFIG_SYS_LATCH_BASE 0x7f200000
230#define CONFIG_SYS_EBC_PB3AP 0x92015480
231#define CONFIG_SYS_EBC_PB3CR 0x7f21a000
232
233#define CONFIG_SYS_LATCH0_RESET 0xffff
234#define CONFIG_SYS_LATCH0_BOOT 0xffff
235#define CONFIG_SYS_LATCH1_RESET 0xffbf
236#define CONFIG_SYS_LATCH1_BOOT 0xffff
237
238#endif
239