LXR uboot/include/galileo/core.h

   1/* Core.h - Basic core logic functions and definitions */
   2
   3/* Copyright Galileo Technology. */
   4
   5/*
   6DESCRIPTION
   7This header file contains simple read/write macros for addressing
   8the SDRAM, devices, GT`s internal registers and PCI (using the PCI`s address
   9space). The macros take care of Big/Little endian conversions.
  10*/
  11
  12#ifndef __INCcoreh
  13#define __INCcoreh
  14
  15/* includes */
  16#include "gt64260R.h"
  17#include <stdbool.h>
  18
  19extern unsigned int INTERNAL_REG_BASE_ADDR;
  20
  21/*
  22 * GT-6426x variants
  23 */
  24#define GT_64260        0  /* includes both 64260A and 64260B */
  25#define GT_64261        1
  26
  27#if (CONFIG_SYS_GT_6426x == GT_64260)
  28#ifdef CONFIG_ETHER_PORT_MII
  29#define GAL_ETH_DEVS 2
  30#else
  31#define GAL_ETH_DEVS 3
  32#endif
  33#elif (CONFIG_SYS_GT_6426x == GT_64261)
  34#define GAL_ETH_DEVS 2
  35#else
  36#define GAL_ETH_DEVS 3  /* default to a 64260 */
  37#endif
  38
  39/****************************************/
  40/*          GENERAL Definitions                 */
  41/****************************************/
  42
  43#define NO_BIT          0x00000000
  44#define BIT0            0x00000001
  45#define BIT1            0x00000002
  46#define BIT2            0x00000004
  47#define BIT3            0x00000008
  48#define BIT4            0x00000010
  49#define BIT5            0x00000020
  50#define BIT6            0x00000040
  51#define BIT7            0x00000080
  52#define BIT8            0x00000100
  53#define BIT9            0x00000200
  54#define BIT10           0x00000400
  55#define BIT11           0x00000800
  56#define BIT12           0x00001000
  57#define BIT13           0x00002000
  58#define BIT14           0x00004000
  59#define BIT15           0x00008000
  60#define BIT16           0x00010000
  61#define BIT17           0x00020000
  62#define BIT18           0x00040000
  63#define BIT19           0x00080000
  64#define BIT20           0x00100000
  65#define BIT21           0x00200000
  66#define BIT22           0x00400000
  67#define BIT23           0x00800000
  68#define BIT24           0x01000000
  69#define BIT25           0x02000000
  70#define BIT26           0x04000000
  71#define BIT27           0x08000000
  72#define BIT28           0x10000000
  73#define BIT29           0x20000000
  74#define BIT30           0x40000000
  75#define BIT31           0x80000000
  76
  77#define _1K             0x00000400
  78#define _2K             0x00000800
  79#define _4K             0x00001000
  80#define _8K             0x00002000
  81#define _16K            0x00004000
  82#define _32K            0x00008000
  83#define _64K            0x00010000
  84#define _128K           0x00020000
  85#define _256K           0x00040000
  86#define _512K           0x00080000
  87
  88#define _1M             0x00100000
  89#define _2M             0x00200000
  90#define _3M             0x00300000
  91#define _4M             0x00400000
  92#define _5M             0x00500000
  93#define _6M             0x00600000
  94#define _7M             0x00700000
  95#define _8M             0x00800000
  96#define _9M             0x00900000
  97#define _10M            0x00a00000
  98#define _11M            0x00b00000
  99#define _12M            0x00c00000
 100#define _13M            0x00d00000
 101#define _14M            0x00e00000
 102#define _15M            0x00f00000
 103#define _16M            0x01000000
 104
 105#define _32M            0x02000000
 106#define _64M            0x04000000
 107#define _128M           0x08000000
 108#define _256M           0x10000000
 109#define _512M           0x20000000
 110
 111#define _1G             0x40000000
 112#define _2G             0x80000000
 113
 114/* Little to Big endian conversion macros */
 115
 116#ifdef LE /* Little Endian */
 117#define SHORT_SWAP(X) (X)
 118#define WORD_SWAP(X) (X)
 119#define LONG_SWAP(X) ((l64)(X))
 120
 121#else    /* Big Endian */
 122#define SHORT_SWAP(X) ((X <<8 ) | (X >> 8))
 123
 124#define WORD_SWAP(X) (((X)&0xff)<<24)+      \
 125                    (((X)&0xff00)<<8)+      \
 126                    (((X)&0xff0000)>>8)+    \
 127                    (((X)&0xff000000)>>24)
 128
 129#define LONG_SWAP(X) ( (l64) (((X)&0xffULL)<<56)+               \
 130                            (((X)&0xff00ULL)<<40)+              \
 131                            (((X)&0xff0000ULL)<<24)+            \
 132                            (((X)&0xff000000ULL)<<8)+           \
 133                            (((X)&0xff00000000ULL)>>8)+         \
 134                            (((X)&0xff0000000000ULL)>>24)+      \
 135                            (((X)&0xff000000000000ULL)>>40)+    \
 136                            (((X)&0xff00000000000000ULL)>>56))
 137
 138#endif
 139
 140#ifndef NULL
 141#define NULL 0
 142#endif
 143
 144/* Those two definitions were defined to be compatible with MIPS */
 145#define NONE_CACHEABLE          0x00000000
 146#define CACHEABLE                       0x00000000
 147
 148/* 750 cache line */
 149#define CACHE_LINE_SIZE 32
 150#define CACHELINE_MASK_BITS (CACHE_LINE_SIZE - 1)
 151#define CACHELINE_ROUNDUP(A) (((A)+CACHELINE_MASK_BITS) & ~CACHELINE_MASK_BITS)
 152
 153/* Read/Write to/from GT`s internal registers */
 154#define GT_REG_READ(offset, pData)                                          \
 155*pData = ( *((volatile unsigned int *)(NONE_CACHEABLE |                     \
 156                INTERNAL_REG_BASE_ADDR | (offset))) ) ;                                              \
 157*pData = WORD_SWAP(*pData)
 158
 159#define GTREGREAD(offset)                                                   \
 160         (WORD_SWAP( *((volatile unsigned int *)(NONE_CACHEABLE |            \
 161                   INTERNAL_REG_BASE_ADDR | (offset))) ))
 162
 163#define GT_REG_WRITE(offset, data)                                          \
 164*((unsigned int *)( INTERNAL_REG_BASE_ADDR | (offset))) =                   \
 165                    WORD_SWAP(data)
 166
 167/* Write 32/16/8 bit */
 168#define WRITE_CHAR(address, data)                                           \
 169        *((unsigned char *)(address)) = data
 170#define WRITE_SHORT(address, data)                                          \
 171        *((unsigned short *)(address)) = data
 172#define WRITE_WORD(address, data)                                           \
 173        *((unsigned int *)(address)) = data
 174
 175/* Read 32/16/8 bits - returns data in variable. */
 176#define READ_CHAR(address, pData)                                           \
 177        *pData = *((volatile unsigned char *)(address))
 178
 179#define READ_SHORT(address, pData)                                          \
 180        *pData = *((volatile unsigned short *)(address))
 181
 182#define READ_WORD(address, pData)                                           \
 183        *pData = *((volatile unsigned int *)(address))
 184
 185/* Read 32/16/8 bit - returns data direct. */
 186#define READCHAR(address)                                                   \
 187        *((volatile unsigned char *)((address) | NONE_CACHEABLE))
 188
 189#define READSHORT(address)                                                  \
 190        *((volatile unsigned short *)((address) | NONE_CACHEABLE))
 191
 192#define READWORD(address)                                                   \
 193        *((volatile unsigned int *)((address) | NONE_CACHEABLE))
 194
 195/* Those two Macros were defined to be compatible with MIPS */
 196#define VIRTUAL_TO_PHY(x)    (((unsigned int)x) & 0xffffffff)
 197#define PHY_TO_VIRTUAL(x)    (((unsigned int)x) | NONE_CACHEABLE)
 198
 199/*  SET_REG_BITS(regOffset,bits) -
 200   gets register offset and bits: a 32bit value. It set to logic '1' in the
 201   internal register the bits which given as an input example:
 202   SET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic
 203   '1' in register 0x840 while the other bits stays as is. */
 204#define SET_REG_BITS(regOffset,bits) \
 205        *(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR |  \
 206        regOffset) |= (unsigned int)WORD_SWAP(bits)
 207
 208/*  RESET_REG_BITS(regOffset,bits) -
 209   gets register offset and bits: a 32bit value. It set to logic '0' in the
 210   internal register the bits which given as an input example:
 211   RESET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic
 212   '0' in register 0x840 while the other bits stays as is. */
 213#define RESET_REG_BITS(regOffset,bits) \
 214        *(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR   \
 215        | regOffset) &= ~( (unsigned int)WORD_SWAP(bits) )
 216
 217#endif /* __INCcoreh */
 218