LXR uboot/arch/powerpc/cpu/mpc85xx/t1040

   1/*
   2 * Copyright 2012 Freescale Semiconductor, Inc.
   3 *
   4 * SPDX-License-Identifier:     GPL-2.0+
   5 */
   6
   7#include <common.h>
   8#include <asm/fsl_serdes.h>
   9#include <asm/processor.h>
  10#include <asm/io.h>
  11
  12
  13static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
  14        [0x00] = {PCIE1, PCIE1, PCIE1, PCIE1,
  15                PCIE2, PCIE2, PCIE2, PCIE2},
  16        [0x06] = {PCIE1, PCIE1, PCIE1, PCIE1,
  17                PCIE2, PCIE3, PCIE4, SATA1},
  18        [0x08] = {PCIE1, PCIE1, PCIE1, PCIE1,
  19                PCIE2, PCIE3, SATA2, SATA1},
  20        [0x40] = {PCIE1, PCIE1, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  21                PCIE2, PCIE2, PCIE2, PCIE2},
  22        [0x60] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
  23                PCIE2, PCIE2, PCIE2, PCIE2},
  24        [0x66] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
  25                PCIE2, PCIE3, PCIE4, SATA1},
  26        [0x67] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
  27                PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
  28        [0x69] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
  29                PCIE2, PCIE3, SGMII_FM1_DTSEC4, SATA1},
  30        [0x86] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  31                PCIE2, PCIE3, PCIE4, SATA1},
  32        [0x85] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  33                PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
  34        [0x87] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  35                PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
  36        [0x89] = {PCIE1, QSGMII_SW1_A, QSGMII_SW1_A, QSGMII_SW1_A,
  37                PCIE2, PCIE3, QSGMII_SW1_B, SATA1},
  38        [0x8D] = {PCIE1, QSGMII_SW1_A, QSGMII_SW1_A, QSGMII_SW1_A,
  39                PCIE2, QSGMII_SW1_B, QSGMII_SW1_B, QSGMII_SW1_B},
  40        [0x8F] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  41                AURORA, NONE, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
  42        [0xA5] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  43                PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
  44        [0xA7] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  45                 PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
  46        [0xAA] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  47                 PCIE2, PCIE3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
  48};
  49
  50enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
  51{
  52        return serdes_cfg_tbl[cfg][lane];
  53}
  54
  55int is_serdes_prtcl_valid(int serdes, u32 prtcl)
  56{
  57        int i;
  58
  59        if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
  60                return 0;
  61
  62        for (i = 0; i < SRDS_MAX_LANES; i++) {
  63                if (serdes_cfg_tbl[prtcl][i] != NONE)
  64                        return 1;
  65        }
  66
  67        return 0;
  68}
  69